Power Up Handshake with FPGA Transceiver

Before starting the operation of the Ethernet 10G MAC core, a power-up handshake must be performed with the FPGA transceiver.

The Ethernet 10G MAC core includes a built-in power-up sequence module to handshake with the FPGA transceiver PHY. For the details on the power-up sequence in the FPGA transceiver, refer to the power-up sequence chapter of the Titanium Ethernet 10GBase-KR User Guide. Figure 1 shows the power-up handshake between the Ethernet 10G MAC core and the FPGA transceiver.

The power-up sequence between the Ethernet 10G MAC core and the FPGA transceiver PHY is clocked by init_clk. The assertion of phy_init_done indicates that the FPGA transceiver PHY is CDR-locked-to-data.