Resource Utilization
Note: The resources and performance values provided are based on some
of the supported FPGAs. These values are just guidance and may change depending on the
device resource utilization, design congestion, and user design.
| FPGA | Mode | Logic Elements (Logic, Adders, Flipflops, etc.) | Memory Blocks | DSP Blocks | Efinity® Version |
|---|---|---|---|---|---|
| Ti375N1156 C4 | Cut Through | 7,190/362,880 (1.98 %) | 0/2,688 (0.19 %) | 0/1,344 (0 %) | 2025.1 |
| Store Forward | 9,479/362,880 (2.61%) | 5/2,688 (0.30 %) | 0/1,344 (0 %) |
Note: The resource utilization data is derived based on the
default settings.
1 System Verilog 2005.