Efinix, Inc.
  • Install Software and SoC
    • Install the Efinity Software
    • Install the Efinity RISC-V Embedded Software IDE
  • IP Manager
    • Customizing the Sapphire High-Performance SoC
    • Modify the Bootloader
  • Recommended Design Practice
  • Example Design
    • About the Example Design
    • Enable the LPDDR4x Memory (Ti375 C529 Board)
    • Installing USB Drivers
    • Program the Development Board
  • Launch Efinity RISC-V Embedded Software IDE
    • Launching the Efinity RISC-V Embedded Software IDE
    • IDE Launcher from Efinity
    • Optimization Settings
  • Create, Import, and Build a Software Project
    • Create a New Project
    • Import Sample Projects
    • Build
  • Debug with the OpenOCD Debugger
    • Launch the Debug Script
    • Debug
    • Debug - Multiple Cores
      • Debug - SMP
    • Peripheral Register View
    • CSR Register View
    • FreeRTOS View
    • QEMU Emulator
  • Concurrent Debugging
    • Enable Concurrent Debugging
    • Disable Concurrent Debugging
    • Concurrent Debugging with Multiple Devices
    • Semihosting with Concurrent Debugging
  • Boot Sequence
    • Boot Sequence: Case A
    • Boot Sequence: Case B
    • Boot Sequence: Case C
    • Booting Multiple Cores
  • Create Your Own RTL Design
    • Target another FPGA
    • Target Your Own Board
  • Create Your Own Software
    • Deploying an Application Binary
      • Boot from a Flash Device
      • Boot from the OpenOCD Debugger
      • Copy a User Binary to Flash (Efinity Programmer)
    • About the Board Specific Package
    • Address Map
    • Example Software
      • clintTimerInterruptDemo
      • coremark
      • customInstructionDemo
      • dCacheFlushDemo
      • dhrystone Example
      • fatFSDemo
      • FreeRTOS Examples
      • fpuDemo
      • gpioDemo
      • iCacheFlushDemo
      • inlineAsmDemo
      • lwipIperfServer
      • memTest Example
      • nestedInterruptDemo
      • oob Example
      • i2cMasterDemo Design
      • i2cMasterInterruptDemo Design
      • i2cSlaveDemo Design
      • rtcDemo
      • sdhcDemo
      • semihostingDemo
      • smpDemo
      • temperatureSensorDemo
      • uartEchoDemo
      • UartInterruptDemo
      • userTimerDemo
  • Hardware and Software Migration from Sapphire SoC to Sapphire High-Performance SoC
    • Introduction
    • Hardware
    • Software
  • Third-party Debugger
  • Watchdog Timer
    • Introduction
    • Functional Description
    • Setting Limits for Both Counters
  • Using a UART Module
    • Using the On-board UART
    • Open a Terminal
    • Enable Telnet on Windows
  • Unified Printf
    • Bsp_print
    • Bsp_printf
    • Bsp_printf_full
    • Semihosting Printing
    • Preprocessor Directives
  • Using a Soft JTAG Core for Example Designs
    • Enabling Soft JTAG in Static Example Design
  • Troubleshooting
    • OpenOCD Error: timed out while waiting for target halted
    • Efinity Debugger Crashes when using OpenOCD
    • Non-existing file for the co_debug_register external tool
    • Error in Final Launch Sequence
    • Debug Core UUID Mismatch
    • Variable references empty selection: ${project_loc}
  • API Reference
    • Control and Status Registers
    • GPIO API Calls
    • I2C API Calls
    • I/O API Calls
    • Core Local Interrupt Timer API Calls
    • User Timer API Calls
    • PLIC API Calls
    • SPI API Calls
    • SPI Flash Memory API Calls
    • UART API Calls
    • RISC-V API Calls
    • Handling Interrupts
  • Inline Assembly
    • Introduction
    • Inline Assembly Syntax
      • Operands
    • RISC-V Registers

Debug with the OpenOCD Debugger

About this task

With the development board programmed and the software built, you are ready to configure the OpenOCD debugger and perform debugging. These instructions use the gpioDemo example to explain the steps required.

  • Launch the Debug Script
  • Debug
  • Debug - Multiple Cores
  • Peripheral Register View
  • CSR Register View
  • FreeRTOS View
  • QEMU Emulator

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