RISC-V Registers
RISC-V has the following 32-bit registers:
- 32 general-purpose registers
- A program counter (PC)
A 32 general-purpose registers have the following assigned functions:
- x0 is hard-wired to 0 and can be used as a target register for any instructions where the result must be discarded.
- x0 can also be used as a source of zero (0) if needed.
- x1-x31 are general-purpose registers. The 32-bit integers they hold are interpreted, depending on the instruction.
A PC has the following assigned functions and characteristics:
- PC points to the next instruction to be executed.
- The PC cannot be written or read using load/store instructions.
The following figure shows the 32 general-purpose registers in a RISC-V ISA1 CPU.Figure 1. RISC-V Base Unprivileged Integer Register State
Calling Convention for RISC-V Registers
The symbolic name in the table is the name used by the RISC-V register when applying the inline assembly in the design.
| Register Name | Symbolic Name | Description |
|---|---|---|
| x0 | Zero | Hardwired zero register, always read as zero (0), and writes are ignored. |
| x1 | Ra | Return address register, used to store the return address. |
| x2 | Sp | Stack pointer register, used to point to the top of the call stack. |
| x3 | Gp | Global pointer register, used to addressing global data. |
| x4 | Tp | Thread pointer, used for addressing thread-local data. |
| x5 | t0 | Temporary register/alternate link register, used for general temporary storage. |
| x6-x7 | t1-t2 | Temporary registers, used for general temporary storage. |
| x8 | s0/fp | Saved register/frame pointer, often used to establish and maintain stack frames. |
| x9 | s1 | Saved register, used for saving and restoring values across function calls. |
| x10-x11 | a0-a1 | Function argument registers/return value register. |
| x12-x17 | a2-a7 | Function argument registers. |
| x18-x27 | s2-s11 | Saved registers, used for saving and restoring values across function calls. |
| x28-x31 | t3-t6 | Temporary registers, often used for general temporary storage. |
Note: Ensure correct registers are used when designing your
program to avoid any data corruption.
1 ISA:
Instruction Set Architecture