Concurrent Debugging

On Efinix FPGA development kits, the hard JTAG controller is usually connected to one of the FTDI channels and used for RTL debugging. Hence, to debug RTL and RISC-V concurrently, you need to configure GPIO pins as a JTAG interface to debug the RISC-V core. Beginning with Efinity RISC-V Embedded software IDE v2025.2, an additional debug flow is introduced, which is known as concurrent debugging. In concurrent debugging mode, both RTL and RISC-V debugging can be done simultaneously via a single FTDI JTAG interface.