Address Map

Because the address range might be updated, Efinix recommends that you always refer to the parameter name when referencing an address in firmware, not by the actual address. The parameter names and address mappings are defined in /embedded_sw/<module>/bsp/efinix/EfxSapphireSoc/include/soc.h.

Note: If you need to update the address map, use the IP Configuration wizard to change the addressing and then re-generate the SoC. Using this method keeps the software soc.h and FPGA netlist definitions aligned.
Table 1. Default Address Map, Interrupt ID, and Cached ChannelsThe AXI user master channel is in a cacheless region (I/O) for compatibility with AXI-Lite.
Device Parameter Size Interrupt ID Region
Off-chip memory SYSTEM_DDR_BMB 3.7 GB – Cache
AXI user master SYSTEM_AXI_A_BMB 256 MB – I/O
User timer 0 SYSTEM_USER_TIMER_0_CTRL 4 K 19 I/O
User timer 1 SYSTEM_USER_TIMER_1_CTRL 4 K 20 I/O
CLINT timer SYSTEM_CLINT_CTRL 4 K – I/O
PLIC SYSTEM_PLIC_CTRL 4 MB – I/O
On-chip BRAM SYSTEM_RAM_A_BMB 16 KB – Cache
External interrupt – – [A]: 1
[B]: 2
[C]: 3
[D]: 4
[E]: 5
[F]: 6
[G]: 7
[H]: 8
[I]: 9
[J]: 10
[K]: 11
[L]: 12
[M]: 13
[N]: 14
[O]: 15
[P]: 16
[Q]: 17
[R]: 18
[S]: 19
[T]: 20
[U]: 21
[V]: 22
[W]: 23
[X]: 24
 I/O
When accessing the addresses in the I/O region, type casting the pointer with the keyword volatile. The compiler recognizes this as a memory-mapped I/O register without optimizing the read/write access. An example of the casting is shown by the following command:
*((volatile u32*) address);

For the cached regions, the burst length is equivalent to an AXI burst length of 8. For the I/O region, the burst length is equivalent to an AXI burst length of 1. The AXI user master is compatible with AXI-Lite by disconnecting unused outputs and driving a constant 1 to the input port.

Note: The RISC-V GCC compiler does not support user address spaces starting at 0x0000_0000.

The following figure shows the default address map and the corresponding software parameters for modules in the memory space.

Figure 1. Sapphire High-Performance Memory Space

The following figure shows the default address map and the corresponding software parameters for I/O.

Figure 2. Sapphire High-Performance APB3 I/O Space (Offset 0xF8000000 – 16 MB)

Figure 3. Sapphire High-Performance AXI4 I/O Space (Offset 0xE8000000 – 256 MB)