Customizing the Sapphire High-Performance SoC

You customize the Sapphire High-Performance SoC using the IP Configuration wizard. The parameters are arranged on tabs so you can click through them more easily.

Table 1. Sapphire High-Performance Hardened RISC-V Device Selection Tab
Parameter	Options	Description
Family	Titanium, Topaz	Device Family Selection. Note: If you are updating your Topaz project with the SLB software version that is lower than v1.19, you are recommended to regenerate the SLB again when the software is updated to v1.19.
Package	484, 529, 900, 1156	Package selection. Current supported package for Topaz: 484, 529 Current supported package for Titanium: All pakcage

Table 2. Sapphire High-Performance Hardened RISC-V Block Tab Parameters
Parameter	Options	Description
JTAG Debug Interface	FPGA User Tap, JTAG with GPIO	Choose whether to include a soft debug TAP for debugging. FPGA User Tap: The SoC uses the JTAG User Tap interface block to communicate with the OpenOCD debugger. JTAG with GPIO: The SoC has a soft JTAG interface to communicate with the OpenOCD debugger.
FPGA User Tap Port	JTAG_USER1, JTAG_USER2, JTAG_USER3, JTAG_USER4	Choose the tap port to target with the OpenOCD debugger. This option only applies when using the JTAG user tap interface block to communicate with the OpenOCD debugger.
AXI4 Slave Interface	On, off	On: Instantiate the interface. Off: Do not use the interface. Note: The Efinity software v2025.2 and higher uses AXI slave instead of AXI master as the interface name.
AXI4 Master Interface	On, off	On: Instantiate the interface. Off: Do not use the interface. This interface is forcibly enabled for peripheral interfacing. Note: The Efinity software v2025.2 and higher uses AXI master instead of AXI slave as the interface name.
CPU n Custom Instruction Interface	On, off	On: Instantiate the interface. Off: Do not use the interface.
AXI Interface Pipeline	On, off	Enable the pipeline for Soc AXI Memory Interface.
AXI Write Buffer	On, off	Bypass the AXI write buffer.
User Interrupt Ports	0 - 24	0: Do not use interrupt port. 1 - 24: The number of interrupt port that turns on.
OCR Application	On, off	On: Overwrite the default SPI flash bootloader with the user application. Off: Initialize SoC without user application.
User Application	–	Enter the path to your target user application. The file must be in `.hex` format.

Table 3. Sapphire High-Performance Soft Logic Block Tab Parameters
Parameter	Options	Description
Peripheral Interconnect	On, off	On: Instantiate an interconnect with peripherals attached to it. Off: Do not use the interconnect generated by the IP Manager.
Pin Resource Assignment	On, off	On: Update project peri.xml to instantiate required GPIO blocks for enabled peripherals. Off: Do not update project peri.xml
Pin Assignment	On, off	On: Update project peri.xml to assign pre-defined pins to GPIO blocks. Off: Do not update project peri.xml.
Required SoC Interrupt Ports	–	Show required interrupts for enabled peripherals.
Uart Controller n	On, off	On: Instantiate the controller. Off: Do not use the controller.
SPI Controller n	On, off	On: Instantiate the controller. Off: Do not use the controller.
I2C Controller n	On, off	On: Instantiate the controller. Off: Do not use the controller.
GPIO Controller n	On, off	On: Instantiate the controller. Off: Do not use the controller.
Specify GPIO n pin width	4, 8, 16, 24, 32	Specify the number of pins to be enabled for the GPIO controller.
Watchdog Timer	On, off	On: Instantiate the watchdog timer. Off: Do not use the watchdog timer.
APB3 interface n	On, off	On: Instantiate the interface. Off: Do not use the interface.
Specify APB3 n size	4 KB, 16 KB, 64 KB, 256 KB, 1 MB	Specify the size of the APB interface.
SD Host Controller	On, off	Instantiate SD host controller ip and integrate into soc wrapper file the interface. To be supported in the upcoming 2024.1 patch release.
Triple-speed Ethernet MAC	On, off	Instantiate ethernet controller ip and integrate into soc wrapper file. To be supported in the upcoming 2024.1 patch release.

Table 4. Sapphire High-Performance PLL Configuration Tab Parameters
Parameter	Options	Description
System Clock PLL
Pin Assignment	On, off	On: Update project peri.xml to include this PLL. Off: Do not update project peri.xml
Instance Name	Fixed string	The PLL instance name will be configured later in the Interface Designer.
PLL Resource	PLL_BL0, PLL_BL1, PLL_BL2	Choose which PLL resource you want to utilize in Interface Designer.
PLL External Clock Source	Clock 0, Clock 1	Specify which external clock source as reference clock to PLL.
Reference Clock Frequency	Input value in MHz	Specify reference clock frequency.
System Clock Frequency	250 - 1000 MHz	Specify the system clock frequency that drives most of the logic of the hardened RISC-V block including CPU, FPU, MMU, caches, on-chip RAM, etc.
Memory Clock Frequency	25 - 250 MHz	Specify the memory clock frequency that drives the AXI traffic to external memory.
DDR Clock Frequency	200 - 900 MHz	Specify the DDR clock frequency that is input to the DDR controller.
Peripheral Clock PLL
Pin Assignment	On, off	On: Update project peri.xml to include this PLL. Off: Do not update project peri.xml
Instance Name	Fixed string	The PLL instance name that will be configured later in the Interface Designer.
PLL Resource	PLL_BLn, PLL_BRn PLL_TLn PLL_TRn,	Choose which PLL resource you want to utilize in Interface Designer. The PLL resource cannot be the same as system clock PLL.
PLL External Clock Source	Clock 0 Clock 1	Specify which external clock source as reference clock to PLL.
Reference Clock Frequency	Input value in MHz	Specify reference clock frequency.
Peripheral Clock	25 - 250 MHz	Specify peripheral clock frequency that drives soft logic block logic.
AXI4 Slave Clock	25 - 250 MHz	Specify AXI4 slave clock.
Custom Instruction Clock	25 - 250 MHz	Specify custom instruction clock frequency.

Table 5. Sapphire High-Performance LPDDR4 Configuration Tab Parameters
Parameter	Options	Description
Device Setting
LPDDR4 Controller Assignment	On, off	On: Update project peri.xml to include this configuration. Off: Do not update project peri.xml
Instance Name	Fixed string	The DDR instance name will be configured later in the Interface Designer.
Memory Data Width	16, 32	The DDR device data width.
Memory Density	2 GB, 3 GB, 4 GB, 6 GB, 8 GB, 12 GB, 16 GB	The DDR device memory density.
Memory Type	LPDDR4, LPDDR4x	The DDR device memory type. Topaz device only supports LPDDR4 memory type with maximum clock frequency of 600 MHz.
Memory Physical Rank	1, 2	The DDR device memory physical rank.

Table 6. Sapphire High-Performance Embedded Software Configuration
Parameter	Options	Description
FTDI Type	Single Channel Dual Channel Quad Channel	Specify the number of channels available for the FTDI device use.
FTDI Debug Channel	Channel 0,Channel 1, Channel 2,Channel 3	Specify which channel the JTAG connected.
Application Size	124 KB, 252 KB, 324 KB, 508 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB, 256 MB, Custom	Specify the size allocated for application in linker scripts.
Application Size (KB)	–	Specify the custom size allocated for application in linker scripts.
Stack Size	1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB, 512 KB, Custom	Specify the size allocated for application stack in linker scripts.
Stack Size (KB)	–	Specify the custom size allocated for application stack in linker scripts.