Sapphire SoC DS Sapphire SoC UG Sapphire HP SoC DS Sapphire HP SoC UG RISC-V Embedded IDE UG Board Support Package
  • Sapphire HP RISC-V SoC Hardware Software UG
  • Introduction
    • Efinity RISC-V Embedded Software IDE
    • Required Software
    • Required Hardware
    • Comparison with Sapphire SoC
    • Performance
  • Install Software and SoC
    • Install the Efinity Software
    • Install the Efinity RISC-V Embedded Software IDE
  • IP Manager
    • Customizing the Sapphire High-Performance SoC
    • Modify the Bootloader
  • Recommended Design Practice
  • Example Design
    • About the Example Design
    • Enable the LPDDR4x Memory (Ti375 C529 Board)
    • Installing USB Drivers
    • Program the Development Board
  • Watchdog Timer
    • Introduction
    • Functional Description
    • Setting Limits for Both Counters
  • Using a UART Module
    • Using the On-board UART
    • Open a Terminal
    • Enable Telnet on Windows
  • Unified Printf
    • Bsp_print
    • Bsp_printf
    • Bsp_printf_full
    • Semihosting Printing
    • Preprocessor Directives
  • Using a Soft JTAG Core for Example Designs
    • Enabling Soft JTAG in Static Example Design
  • Troubleshooting
    • OpenOCD Error: timed out while waiting for target halted
    • Efinity Debugger Crashes when using OpenOCD
    • Non-existing file for the co_debug_register external tool
    • Error in Final Launch Sequence
    • Debug Core UUID Mismatch
    • Variable references empty selection: ${project_loc}
  • API Reference
    • Control and Status Registers
    • GPIO API Calls
    • I2C API Calls
    • I/O API Calls
    • Core Local Interrupt Timer API Calls
    • User Timer API Calls
    • PLIC API Calls
    • SPI API Calls
    • SPI Flash Memory API Calls
    • UART API Calls
    • RISC-V API Calls
    • Handling Interrupts
  • Inline Assembly
    • Introduction
    • Inline Assembly Syntax
      • Operands
    • RISC-V Registers

Watchdog Timer

  • Introduction
  • Functional Description
  • Setting Limits for Both Counters