About the Example Design

This example targets Titanium development boards:

  • Titanium Ti375 C529 Development Board—The RTL design files are in the Ti375C529_devkit directory.
When you generate the IP core, the IP Manager creates the example design (PLL settings, SDC timing constraints, and I/O assignments).

This example writes to and reads from the development board's memory module using the AXI interface:

  • For the Titanium Ti375 C529 Development Board, the design uses the board's LPDDR4/LPDDR4x DRAM module.
The Sapphire High-Performance SoC is configured for:
  • 1000 MHz system clock frequency
  • 250 MHz memory clock frequency
  • 800 MHz DDR controller clock frequency
  • 200 MHz peripheral clock frequency
  • 250 MHz AXI slave clock frequency
  • 125 MHz custom instruction clock frequency
  • Used FPGA user tap 1 for debugging
  • Custom instruction for each CPU is enabled
  • UART 0 is enabled
  • SPI 0 is enabled
  • I2C 0 is enabled
  • GPIO 0 is enabled
  • AXI4 Master is enabled
  • AXI Slave 0 is enabled
  • 8 User interrupts are enabled

Additional soft IPs like AXI interconnect, SD host controller and ethernet controller are included in the example design.

Figure 1. Example Design Block Diagram
Table 1. Example Design Implementation
FPGA Logic + Adders Flipflops Multipliers
or DSP Blocks
 Memory Blocks fMAX (MHz) Language Efinity Version
Ti375 BGA529 C4 14,987 11,858 0 76 233 Verilog HDL 2024.1