AN 044: Aligning LVDS Clock and Data Signals in Trion Devices

Introduction

FPGAs support LVDS TX (transmit) and RX (receive) channels for high-speed and noise-tolerant data transmission. This application note describes how to align the clock and data for LVDS interface in different applications.

Trion LVDS Feature Summary

The following table summarizes the LVDS interface features in Trion FPGAs related to the scope of this application note. Refer to the respective device data sheets for detailed LVDS specifications.

Table 1. Trion LVDS Feature Summary
Feature	Notes
Mode	Half-rate only.
Serialization width	Up to 8:1, 7:1, 6:1, 5:1, 4:1, 3:1, 2:1
Delay modes
Dynamic phase alignment	Not supported
Serialization	Half-rate only
Maximum data rate per channel	800 Mbps 600 Mbps (Center-Aligned)

Notice: Refer to the device data sheet table “Maximum Toggle Rate” for detailed data rate specifications that vary with speed grade.

Hardware Design

High-speed differential signal quality is sensitive and strongly affected by the board design. You must consider trace routing, impedance matching, and crosstalk in both the schematic and PCB design when planning a board design with high-speed differential signals.

Observe the following design best practices when implementing LVDS data transmission:

Use LVDS blocks from the same side of the FPGA to minimize skew between the data lanes, and between the clock and data lanes in an LVDS interface. For example, looking at the package from above, signals sent from or received at the top edge of the chip should utilize LVDS resources located in the top I/O banks. All clock lanes and data lanes associated with the channel should use the GPIOT_PN_<number> pins.
Delay matching is required for all PCB traces in an LVDS transmission channel.

Note: Refer to “Package Net Length” on the Board Design page of the Support Center for the net length and propagation delay for your package.

Notice: Refer to the "LVDS Pin General Guidelines" in the Interactive Hardware Design Checklist and Guideline (LVDS Pin General Guidelines) for more information about designing hardware with LVDS in Efinix FPGAs:

Trion Hardware Design Checklist and Guidelines page of the Support Center

You need a Support Center account to download the Efinity software to be able to view and download board design information.

Understanding LVDS Serialization

LVDS signals are serialized differential signals that are normally sent out synchronously with a differential clock signal. Differential pairs that carry data signals are called data lanes, while differential pairs that carry clock signals are called clock lanes. Data lanes, together with the clock lanes they are synchronized with, create a channel. The following diagram shows how the parallel data serialized on the TX is sent over the wires, received, and deserialized back into parallel data on the RX.

Figure 1. Block Diagram of LVDS TX/RX Implementation on Efinix FPGA

Note: The delay block between the buffer and serializer/deserializer in the figure above has been omitted for the sake of simplicity.

Note: RX PLL must be in core feedback mode. Either rx_slowclk or rx_fastclk can serve as the feedback clock, with your choice based on which is more practical: edge-aligned or center-aligned.

With serialization, you send parallel data at width that varies in accordance with the serialization width. Both a parallel clock and a serial clock from the same PLL are needed for a LVDS block when serialization is enabled. In the figure above, the parallel clock and serial clock are named slowclk and fastclk, respectively. Slowclk is a parallel clock used to load parallel data into the serializer register of the LVDS interface. Slowclk is also the same clock domain as the input/output data received/transmitted to the LVDS interface. Fastclk, on the other hand, is a serial clock used to serialize or deserialize data.

Trion FPGAs

Trion FPGAs only support half-rate LVDS serialization, in which data is sent and received on both the rising and falling edges of the serial clock.

Edge-Aligned Signals

The following sections describe the generation of edge-aligned Tx and Rx signals for Trion FPGAs.

TX Edge-Aligned

The following clocks from a single PLL source must be provided to the LVDS interface for edge-aligned signal generation:

tx_slowclk—Parallel clock LVDS TX blocks, both clock lane and data lanes.
tx_fastclk—Serial clock for LVDS TX blocks, both clock lane and data lanes.

The frequency, phase, and tx_slowclk and tx_fastclk PLL settings are as follows:

Data rate must be equal to or greater than the maximum toggle rate as stated in the data sheet.
tx_slowclk frequency = data rate / serialization width.
tx_fastclk frequency = tx_slowclk frequency × (serialization width ÷ 2).
tx_fastclk phase = 90° shifted with respect to tx_slowclk.
tx_slowclk as the core feedback clock for the PLL.

The tx_fastclk and tx_slowclk relationship is given by the following equations:

Half-rate: tx_fastclk = tx_slowclk × serialization rate ÷ 2.
Full-rate (Titanium only): tx_fastclk = tx_slowclk × serialization rate.

Example:

Scenario:

Trion Device: T120
I/O Standard: LVDS
Serialization Width: 8-to-1
Data Rate: 800 Mbps

Therefore:

tx_slowclk frequency = 800 Mbps ÷ 8 = 100 MHz
tx_fastclk frequency = 100 MHz × (8 ÷ 2) = 400 MHz
tx_slowclk phase = 0°
tx_fastclk phase = 90°
tx_slowclk as core feedback clock signal for PLL

Figure 2. Trion TX Edge-Aligned PLL Settings Example. Serialization Width: 8-to-1; Data Rate: 800 Mbps

Note: The output divider for PLL must be either div4 or div8 when you set the clock output phase to 90°, 180°, or 270°. If you set the PLL in manual mode, then the output divider settings must be corrected to fulfill the constraint check. When using core or local feedback mode, set the F_VCO to above 1.6 GHz to maximize data valid window.

Figure 3. Trion TX Edge-Aligned Waveform. Serialization Width: 8-to-1

RX Edge-Aligned

Note: Core feedback mode is strongly recommended for PLL of LVDS RX to minimize variations of clock network delay among devices.

The following clocks from a single PLL source need to be provided to the LVDS interface for receiving edge-aligned signal:

rx_slowclk—Parallel clock for LVDS RX blocks, data lanes.
rx_fastclk—Serial clock for LVDS RX blocks, data lanes.

The requirements for frequency, phase, rx_slowclk, and rx_fastclk settings in the PLL setup are as follows:

Date rate must be less than or equal to the maximum toggle rate stated in the data sheet.
Set rx_slowclk as the coore feedback clock signal for the PLL.

Table 2. Requirements for Frequency and Phase
	Frequency	Phase
slowclk	Data rate ÷ Deserialization width	0
fastclk	Data rate ÷ 2	90º
feedbackclk (core feedback)	rx_refclk frequency	360º ÷ (2 × deserialization width)

Figure 4. Trion RX Edge-Aligned Waveform. Serialization Width: 8-to-1

Center-Aligned Signals

The following sections describe the generation of center-aligned Tx and Rx signals for Trion FPGAs, as well as providing examples of 7:1 serialization.

TX Center-Aligned

The following clocks from a single PLL source need to be provided to the LVDS TX interface for center-aligned signal generation:

tx_slowclk—Parallel clock for LVDS TX blocks, both clock lane and data lanes.
tx_fastclk_clk—Serial clock for LVDS TX blocks, clock lane.
tx_flastclk_data—Serial clock for LVDS TX blocks, data lanes.

The requirements for frequency, phase, and tx_slowclk, tx_fastclk_clk, and tx_fastclk_data settings in the PLL setup are as follows:

Data rate must be less than or equal to the maximum toggle rate (i.e., 600 Mbps) for center-aligned configuration on Trion FPGAs.
Set tx_slowclk as the core feedback clock signal for the PLL.

Table 3. Requirements for Frequency, Phase, and Settings
	Frequency	Phase
slowclk	data rate ÷ serialization width	0
fastclk_clk	Data rate ÷ 2	135°
fastclk_data	Data rate ÷ 2	45°
feedbackclk (core feedback)	tx_refclk frequency	360º ÷ (2 × serialization width)

Figure 5. Trion TX Center-Aligned Waveform. Serialization Width: 8-to-1

RX Center-Aligned

The connection type for the LVDS RX clock lane is required to set to pll_clkin.

The following clocks from a single PLL source need to be provided to the LVDS RX interface to receive the center-aligned signal:

rx_slowclk—Parallel clock for LVDS RX blocks, data lanes.
rx_fastclk—Serial clock for LVDS RX blocks, data lanes.

The requirements for frequency, phase, rx_slowclk, and rx_fastclk settings in the PLL setup are as follows:

RX_clock_lane_refclk = data rate ÷ serialization width.
Data rate must be less than or equal to the maximum toggle rate stated in the data sheet.
rx_fastclk as core feedback clock signal for the PLL.

Table 4. Requirements for Frequency and Phase
	Frequency	Phase
rx_slowclk	Data rate ÷ Deserialization width	0
rx_fastclk	Data rate ÷ 2	90°
feedbackclk (core feedback)	rx_refclk frequency	360º ÷ (2 × deserialization width)

Figure 6. Trion RX Center-Aligned Waveform. Serialization Width: 8-to-1

7:1 Serialization Examples

When receiving data from Trion LVDS TX, the input clock signal is 1110000 for one data set. You have to set up the clock and PLL depending on the data alignment as described previously.

Figure 7. Trion RX Edge-Aligned Waveform (Data Input from Trion LVDS TX). Serialization Width: 7-to-1

Be aware that many of the sensors available on the market send out edge-aligned LVDS TX data with a clock pattern of 1100011 (i.e., shifted clock pattern), which is different to the Trion LVDS RX clock-data lane’s alignment. Therefore, each 7-bit word received on the Trion LVDS RX interface is in {<current data>[4:0], <previous data>[6:5]} shifted format. Therefore, you need an extra register stage to align the bits in each word to data [6:0] in your RTL design.

Table 5. Trion LVDS TX Serialization Configuration Summary
Serialization Width	Half/Full-Rate	Edge-Align	Center-Align
8	Half	slowclk frequency = data rate ÷ serialization width slowclk phase = 0° fastclk frequency = slowclk frequency × (serialization width ÷ 2) fastclk phase = 90°	slowclk frequency = data rate ÷ serialization width slowclk phase = 0° fastclk data frequency = slowclk frequency × (serialization width ÷ 2) fastclk data phase = 45° fastclk_clk frequency = fastclk data frequency fastclk_clk phase = 135°
7	Half
6	Half
5	Half
4	Half
3	Half
2	Half

slowclk—Shared parallel clock for LVDS TX clock lane and data lanes
fastclk—Shared serial clock for LVDS TX clock lanes and data lanes
fastclk_data—Serial clock for LVDS TX data lanes
fastclk_clk—Serial clock for LVDS TX clock lane

Table 6. Trion LVDS RX Deserialization Configuration Summary
Serialization Width	Half/Full-Rate	Edge-Align	Center-Align
8	Half	slowclk frequency = data rate ÷ deserialization width slowclk phase = 0° fastclk frequency = data rate ÷ 2 fastclk phase = 90° slowclk as PLL core feedback clock signal	slowclk frequency = data rate ÷ deserialization width slowclk phase = 0° fastclk frequency = data rate ÷ 2 fastclk phase = 90° fastclk as PLL core feedback clock signal
7	Half
6	Half
5	Half
4	Half
3	Half
2	Half

slowclk—Parallel clock for LVDS RX data lanes
fastclk—Serial clock for LVDS RX data lanes

Delay Calibration

There is an optimal window that is considered the center point of a valid data sampling window. The source synchronous clock and data signals should arrive at the deserializer inputs at the same time; however, the optimal window can vary depending upon package LVDS lane position (i.e., top/bottom/left/right) and PCB trace design.

Keep in mind that some skew will likely be present due to slight variations in production. Therefore, Efinix strongly recommends calibrating the delay settings for LVDS clock and data alignment to ensure best performance.

Calibrating with Static Delay

To calibrate a static delay process, a known synchronous data pattern is sent via a transmitter to an FPGA, which acts as a receiver. The data pattern consists of a repeating string; for example, deserialization width of 8, cycling 8’h4b, 8’h57, 8’h7c, 8’h3e. The FPGA is loaded with an RTL calibration design that does the word alignment and verifies receipt of the data pattern. Once received data pattern after word aligning is mismatch with the known data pattern, a FAIL signal asserted.

Steps for static delay calibration:

With the calibration design project peripheral design opened in Interface designer, set Static Mode Delay setting for clock lane and all data lanes to 0. (If Trion FPGA is used, also turn on the Enable Delay option).
Save the peripheral design, generate Efinity Constraint Files, and then re-generate bitstream. Synthesis, Place and Route compilation steps can be skipped as no changes are made in RTL design files.
Program FPGA with newly generated bitstream.
Send out the known synchronous data pattern from transmitter, check any received data pattern mismatch with the known data pattern, record down the checker PASS/FAIL result for all data lanes.
Repeat step 2 to 4, by sweeping the Static Mode Delay setting from 0 to 63 for all data lanes.
If two passing window edges are found, select the middle value in the passing window range. For example, with passing window following, the valid range is from 9 to 47; therefore, select the middle value (i.e., 28) for all data lanes.
Formula: middle value = (upper edge – lower edge) ÷ 2 + lower edge.

Figure 8. Static Delay Calibration – Passing Window 1

If valid windows are found at both ends, the passing window is assumed to be a loop. Select the middle value. For example, referring to the passing window following, there are passing ranges on both ends, lower edge = 13, upper edge = 50, select middle value = 0 for all data lanes.
Formula: middle value = lower edge - [(64 – upper edge) + lower edge] ÷ 2.

Figure 9. Static Delay Calibration – Passing Window 2

Note: Bit slip is a condition in which a bit falls into another word (either MSB slipped as LSB of the next word, or LSB slipped as MSB of the previous word, or multiple bits have slipped to another word). Bit slip happens when a clock–data delay mismatch occurs due to PCB traces, reflects as another passing window. in the figure above, TX sends a counter sequence, (8’h28, 8’h29, 8’h2A…), if the passing window on left (step 0 to 13) receives a counter sequence without any bit slip (8’h28, 8’h29, 8’h2A…); therefore, a passing window on the right (step 50 to 63) will receive a counter sequence with one bit slip (8’h50, 8’h52, 8’h56,…) as a word:{d0[6:0], d1[7]}.

If the data rate is 700 Mbps or lower, change the static delay setting for the clock lane to 63 and the sweeping static delay setting from 0 to 63 again for the data lanes. Using the same method as described in step 6 or 7 (depending upon the situation), use the middle value of the passing window. For example in the case of the passing window shown below, select 50 for all data lanes, and 63 for the clock lane.

Figure 10. Static Delay Calibration – Passing Window 3

Repeat the above steps for each part until you have a static delay setting that adequately compensates for any manufacturing variation.

Note: The center point of the passing window is dedicated to the PLL and global clock buffer. If any changes to these settings changes the center point of the window, you might need to screen the passing window again to get a new center point.

Revision History

Table 7. Revision History
Date	Version	Description
February 2026	2.2	Titanium and Topaz information relocated to a new document (AN-074). (DOC-2597)
June 2025	2.1	Updated Calibrating with Dynamic Delay (/ only). (DOC-2531) Fixed typo in Figure 1 and Figure 2. (DOC-2482)
March 2025	2.0	Major update of whole document. (DOC-2333)
August 2024	1.5	Corrected half-rate serialization for Titanium FPGAs. (DOC-1937)
March 2024	1.4	Corrected RX_DLY_RST in dynamic delay waveform (Figure 1). (DOC-1697)
February 2024	1.3	Added description about using LDS blocks from the same FPGA side to minimize skew. (DOC-1150) Updated dynamic delay waveform (Figure 1). (DOC-1697)
February 2023	1.2	Updated Feature Summary table. (DOC-1079) Updated PLL setting description to mention setting the PLL F_VCO above 1.6 GHz. (DOC-1026) Updated Calibrating Titanium FPGAs using DPA topic.
October 2022	1.1	Added DPA example waveform. Added TX center-aligned method information. Added Titanium dynamic and static delay options. Added PLL setup example settings.
May 2022	1.0	Initial release.