AN 070: Understanding SPI Flash Operations in SIP Devices

Introduction

Efinix® provides some FPGAs as SIPs, in which the FPGA is combined with another device, such as flash memory. SIPs that include flash memory make it easy for you to integrate the FPGA on your board because you do not need to include a flash device. Instead, the FPGA configures itself from the flash memory in the package. This application note explains how to use the flash device in SIP packages.

Feature Summary

The following table outlines the range of SPI flash features available in Efinix FPGA’s with SIP devices.

Table 1. Summary of SPI Flash Features in Efinix® FPGA’s with SIP Devices
Device	SPI Active (Internal Flash)	SPI Passive	Cascade SPI Flash on the same SPI Bus	4-Byte Addressing	Number of Images that can be Stored
T13Q100F3, T20Q100F3	x4	x16	Supported	Not Supported	4
Ti135F100S3F2, Ti60F100S3F2	x4	x2	Not Supported	Not Supported	2
Ti135N576D2F4	x4	x32	Supported	Supported	4

SPI Flash Block Interface Features

The T20 and Ti60 comes with 2 MB of SPI flash. The following table outlines the signal connection between the SPI flash interface and FPGA fabric.

Table 2. Interface Mapping
SPI Name	FPGA Pin	Interface to FPGA Fabric
SPI Name	FPGA Pin	x1 Mode (default)	x2 Mode	x4 Mode	Fabric Signal	Fabric Direction
SPI_CS_N	SSL_N	Input	Input	Input	CS_N_OUT	Input
SPI_CS_N	SSL_N	Input	Input	Input	CS_N_OE	Input
SPI_SCLK	CCK	Input	Input	Input	SCLK_OUT	Input
SPI_SCLK	CCK	Input	Input	Input	SCLK_OE	Input
SPI_MOSI	CDI0	Input	Input/Output	Input/Output	MOSI_IN	Output
					MOSI_OUT	Input
					MOSI_OE	Input
SPI_MISO	CDI1	Output	Input/Output	Input/Output	MISO_IN	Output
					MISO_OUT	Input
					MISO_OE	Input
SPI_WP	CDI2	Input	Input	Input/Output	WP_N_IN	Output
					WP_N_OUT	Input
					WP_N_OE	Input
SPI_HOLD_N	CDI3	Input	Input	Input/Output	HOLD_N_IN	Output
					HOLD_N_OUT	Input
					HOLD_N_OE	Input

Refer to SPI flash section of data sheets for supported commands, registers, and address mapping.

The following table shows the Status Register bits supported by the device.

Table 3. Status Registers
Bit	Name	Description	Non-Volatile
0^¹	WIP	1: Indicating whether the memory is busy in program/erase/write status register progress.
1^¹	WEL	1: Enable to accept write commands (Write Status Register, Program, or Erase command).
6^¹ – 2^¹	BP[4:0]	The Block Protect bits define the size of the area to be software protected against Program and Erase commands
8^² – 7^¹	SRP[1:0]	The SRP bits control the method of write protection
		00: Status register S23 – S0 can be written to after a Write Enable command (0x06),
		01: Hardware Protected: WP_N=0: Status registers are locked and cannot be written to. WP_N=1: Status registers are unlocked and can be written to after a Write Enable command (0x06). Note: If QE bit is set to 1, WP# pin will not function.
		10: Command, WEL=1. Power Supply Lock-Down: Status Registers are protected and cannot be written to again until the next Power up cycle.
		11: Not supported
9^²	QE	The Quad Enable (QE) bit allows quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enabled. When the QE pin is set to 1, the quad IO2 and IO3 pins are enabled.
10^²	–	Not available
13^² – 11^²	LB[3:1]	The LB3–LB1bits are one-time programmable. When set to 1, the Security Registers are permanently set to read-only.	OTP
14^²	CMP	Used in conjunction with bits BP4-BP0 to provide greater flexibility for array protection.
15^²	SUS	1: After executing an Program/Erase Suspend (75H) command. 0: By Program/Erase Resume (7AH) command, as well as a power-down, power-up cycle.
16^³	–	Not available (Set to 0)
17^³	–	Not available (Set to 0)
18^³	WPS	0 (default): The device uses the combination of CMP and BP[4:0] bits to protect a specific area of the memory array. 1: The device uses the individual block locks to protect any individual sector or blocks.
19^³	–	Not available (Set to 0)
20^³	–	Not available (Set to 0)
21^³	–	Not available (Set to 0)
22^³	–	Not available (Set to 0)
23^³	HOLD/RST	0: The pin acts as /HOLD 1: The pin acts as /RESET. QE is set to 1, the /HOLD and /RESET functions are disabled, the pin acts as a dedicated data I/O pin.

Note: Status registers S7–S0 are accessed by command 05h and 01h. Status registers S15–S8 are accessed by command 35h and 31h. Status registers S23–S16 are accessed by command 15h and 11h.

SPI Flash Block Interface Support Devices

This section describes the SPI flash interface for Efinix system-in-package (SIP) FPGAs that include an internal SPI flash device.

Packages with CS_N

Trion FPGAs in QFP100F3 packages are a system-in-package (SIP) that includes an internal SPI flash device.

The SPI flash memory VCC is powered by VCCIO1A_1B_1C (3.3 V)⁴. The following figure shows the internal connections and pin assignment. The SPI flash memory stores the configuration bitstream for FPGA SPI active configurations. The SPI flash device is used to store the bitstream. Additionally, in user mode, the SPI flash device can store data sent to it by the FPGA. For a more detailed overview of FPGA hardware design and configuration, refer to AN 006: Configuring Trion FPGAs. The CS pin of the internal SPI flash device is an individual pin in the package. Connect the pin to GPIOL_00_SS_N on the board design if you intend to use the internal flash.

Figure 1. Connections between FPGA and SPI Flash Device inside the Package

Figure 2. Circuit Design using both Internal and External Flash

Note: To program the SPI flash or to enter SPI passive configuration, the off-chip MCU should:

Drive SS_N to low
Drive CRESET_N to low.

Packages without CS_N

Titanium FPGAs in F100F3S2 packages are a system-in-package (SIP) that includes an internal SPI flash device.

The SPI flash memory VCC is connected to VCCIO1A_4B. If you are using the SPI flash memory, drive the VCCIO1A_4B with a 1.8 V supply. The following figure shows the internal connections and pin assignment. The SPI flash memory stores the configuration bitstream for FPGA SPI active configurations. The SPI flash device is used to store the bitstream. Additionally, in user mode, the SPI flash device can store data sent to it by the FPGA. For a more detailed overview of FPGA hardware design and configuration, refer to AN 033: Configuring Titanium FPGAs.

Figure 4. Connections between FPGA and SPI Flash inside the Package

Figure 5. Configuration with Internal Flash

Note: To program the SPI flash or to enter SPI passive configuration, the off-chip MCU should:

Drive SSL_N to low
Drive CRESET_N to low.

Timing and AC Characteristics

The following figures show the timing of serial input/output data transmitted between the FPGA interface (master) and SPI flash device, as well as corresponding AC characteristics.

Table 4. AC Parameters for Interfacing with SPI Flash (T_a = -40°C to +85°C)
Symbol	Parameter	VCC = 1.8 V⁵			VCC = 3.3 V⁶			Unit
Symbol	Parameter	Min.	Typ.	Max.	Min.	Typ.	Max.	Unit
f_SCLK	Clock Frequency			33			55	MHz
t_CLL	Clock High Time	5.5			3.3			ns
t_CLH	Clock Low Time (f_SCLK) 45% x (1f_SCLK)	5.5			3.3			ns
t_CLQX	Output Hold Time	0			0			ns
t_CLQV	Clock Low to Output Valid Loading	7			7			ns
t_SHQZ	Output Disable Time			6			6	ns
t_CHSL	CS# Not Active Hold Time (Relative to SCLK)	5			5			ns
t_SLCH	CS# Active Setup Time (Relative to SCLK)	5			5			ns
t_DVCH	Data in Setup Time	2			2			ns
t_CHDX	Data in Hold Time	3			3			ns
t_CLCH	Clock Rise Time (Peak to Peak)	0.1			0.1			V/ns
t_CHCL	Clock Fall Time (Peak to Peak)	0.1			0.1			V/ns
t_SHSL	CS# Deselect Time from Read to next Read	20			20			ns
t_SHSL	CS# Deselect Time From Write, Erase, Program to Read Status Register	30			30			ns
t_CHHL	HOLD# Not Active Hold Time (Relative to SCLK)	5			5			ns
t_HLCH	HOLD# Active Setup Time (Relative to SCLK)	5			5			ns
t_CHHH	HOLD# Active Hold Time (Relative to SCLK)	5			5			ns
t_HHCH	HOLD# Not Active Setup Time (Relative to SCLK)	5			5			ns
t_HLQZ	HOLD# to Output High-Z			6			6	ns
t_HHQX	Output Hold Time			6			6	ns
t_WHSL	Write Protect Setup Time	20			20			ns
t_SHWL	Write Protect Hold Time	100			100			ns
t_DP	CS# High to Deep Power-down Mode			3			3	us
t_RES1	CS# High to Standby Mode without Electronic Signature Read			8			8	us
t_RES2	CS# High to Standby Mode with Electronic Signature Read			8			8	us
t_W	Write Status Register Cycle Time		8	12		8	12	ms
t_Ready	Reset Recovery Time (for erase/program operation except WRSR)	30			30			us
t_Ready	Reset Recovery Time (for WRSR operation)	12	8		12	8		ms
t_BL	Load memory page data to buffer time (256 Byte)			60			60	us
t_BL	Load memory page data to buffer time (512 Byte)			120			120	us
t_BC	Buffer clear to next instruction latency	300			200			ns

The following waveforms show the timing of hold and WP between the FPGA interface (master) and SPI flash device, as well as corresponding AC characteristics as shown previously.

The following table shows the timing of Program and Erase command operations.

Table 5. AC Parameters for SPI Flash Program and Erase (T_a = -40°C to +85°C)
Symbol	Parameter	VCC = 1.8 V⁷			VCC = 3.3 V⁸			Unit
Symbol	Parameter	Min.	Typ.	Max.	Min.	Typ.	Max.	Unit
TESL	Erase Suspend Latency			30			30	us
TPSL	Program Suspend Latency			30			30	us
TPRS	Latency between Program Resume and Next Suspend	20			20			us
TERS	Latency between Erase Resume and next Suspend	20			20			us
t_PP	Page program time (up to 256 bytes)		2	3		1.5	3	ms
t_PE	Page erase time		16	20		16	30	ms
t_SE	Sector erase time		16	20		16	30	ms
t_BE1	Block erase time for 32K bytes		16	20		16	30	ms
t_BE2	Block erase time for 64K bytes		16	20		16	30	ms
t_CE	Chip erase time		130	180		130	180	ms

Supported Commands

Use the commands in the following table to perform flash device operations (e.g., read, write). Memory access supports 24-bit addressing, with byte addresses assigned via the address frame. The first byte on the frame is at the address [23:16], followed by address [15:8], and with the last byte at address [7:0]. All serial input and output timing frames for standard SPI commands rely on x1 mode timing.

For dual SPI commands, some serial input/output timings rely on x2 mode timing. Pins SPI_MOSI and SPI_MISO are used for either serial input or output. SPI_WP and SPI_HOLD pin functions are available.

For quad SPI commands, some serial input /output timings rely on x4 mode timing. SPI_MOSI, SPI_MISO, SPI_WP and SPI_HOLD are used for either serial input or output. The QE bit of the status registers must be set to 1 before issuing any quad SPI commands. Also, be aware the functions of the SPI_WP and SPI_HOLD pins are unavailable while the QE bit is set to 1.

Table 6. Supporting Commands (Standard SPI)
Commands	Description	Value / Number of Bytes (Mode)
Commands	Description	Op Code (Command)	Address	Dummy	Data Input	Data Output
Status Register
Read Status Register	Read Status Register Bit S7 – S0	05h (x1)			S7 – S0 (x1)
Read Status Register-1	Read Status Register Bit S15 – S8	35h (x1)			S15 – S8 (x1)
Read Configure Register-2	Read Status Register Bit S23 – S16	15h (x1)			S23 – S16 (x1)
Write Status Register	Write to Status Register Bits S7 – S0	01h (x1)				S7 – S0 (x1)
Write Status Register-1	Write to Status Register Bits S15 – S8	31h (x1)				S15 – S8 (x1)
Write Configure Register-2	Write to Status Register Bits S23 – S16	11h (x1)				S23 – S16 (x1)
Read
Read Array	n Bytes Read Until CS# Goes High	03h (x1)	3 (x1)		1+ (x1)
Read Array (Fast)	n Bytes Read Until CS# Goes High	0Bh (x1)	3 (x1)	1 (x1)	1+ (x1)
Read Manufacturer/Device ID	Output JEDEC ID: 1-Byte Manufacturer ID 2-Byte Device ID	9Fh (x1)			1 – 3 (x1)
Read Manufacture ID	Read Manufacturer ID (Odd Address) and Device ID (Even Address)	90h (x1)	3 (x1)		1+ (x1)
Erase/Program
Page Erase	Erase Selected Page	81h (x1)	3 (x1)
Sector Erase (4K Bytes)	Erase Selected Sector	20h (x1)	3 (x1)
Block Erase (32K Bytes)	Erase Selected 32K Block	52h (x1)	3 (x1)
Block Erase (64K Bytes)	Erase Selected 64K Block	D8h (x1)	3 (x1)
Chip Erase	Erase Whole Chip	60h/C7h (x1)
Page Program	Program Selected Page	02h (x1)	3 (x1)			1 – 256 (x1)
Program/Erase Suspend	Suspend Program/erase Operation	75h (x1)
Program/Erase Resume	Suspend Program/Erase Operation	7Ah (x1)
Protection
Write Enable	Sets Write Enable Latch Bit S1 WEL = 1	06h (x1)
Write Disable	Resets Write Enable Latch Bit S1 WEL = 0	04h (x1)
Volatile SR Write Enable	Write Enable for Volatile SR	50h (x1)
Individual Block Lock	Individual Block Lock	36h (x1)	3 (x1)
Individual Block Unlock	Individual Block Lock	39h (x1)	3 (x1)
Read Block Lock Status	Read Individual Block Lock Register	3Dh (x1)	3 (x1)		1+ (x1)
Global Block Lock	Whole Chip Block Protect	7Eh (x1)
Global Block Unlock	Whole Chip Block Unprotect	98h (x1)
Security
Erase Security Registers	Erase Security Registers	44h (x1)	3 (x1)
Program Security Registers	Program Security Registers	42h (x1)	3 (x1)			1+ (x1)
Read Security Registers	Read Value of Security Registers	48h (x1)	3 (x1)		1+ (x1)
Others (Standard SPI)
Reset Enable	Enable Reset	66h (x1)
Reset	Enable Reset	99h (x1)
Deep Power Down	Enters Deep Power-Down Mode	B9h (x1)
Release Deep Power - Down/ Read Electronic ID	Read Eelectronic ID Data	Abh (x1)	3 (x1)		1 (x1)
Read SFDP	Read SFDP Parameter (SFDP is a JEDEC Standard, JESD216B)	5Ah (x1)	3 (x1)	1 (x1)	1+ (x1)

Table 7. Supporting Commands (Dual and Quad SPI)
Commands	Description	Value / Number of Bytes (Mode)
Commands	Description	Op Code (Command)	Address	Dummy	Data Input	Data Output
Read (Dual SPI)
Read Dual Output	n Bytes Read by Dual Output	3Bh (x1)	3 (x1)	1 (x1)	1+ (x2)
Read 2IO	n Bytes Read by 2IO	BBh (x1)	3 (x2)	1 (x1)	1+ (x1)
Dual Read Manufacture ID	Dual Output Manufacture (Odd)/Device ID (Even)	92h (x1)	3 (x2)		1+ (x2)
Read (QUAD SPI)
Read QUAD Output	n bytes read out by quad output	6Bh (x1)	3 (x1)	1 (x1)	1+ (x4)
Read 4IO	n Bytes Read by 4IO	Ebh (x1)	3 (x4)	3 (x4)	1+ (x4)
Read Word 4IO	n Bytes Word Read by 4IO	E7h (x1)	3 (x4)	1 (x4)	1+ (x4)
Quad Read Manufacture ID	Quad Output Manufacture (Odd)/Device ID (Even Address)	94h (x1)	3 (x4)		1+ (x4)
Erase / Program (QUAD SPI)
Quad Page Program	Quad Input to Program Selected Page	32h (x1)	3 (x1)			1 – 256 (x4)

Data Protection

The BP[4:0] and CMP WPS status registers are used to define protected areas of memory. Any commands, whether issued manually by automated by software, to change or erase the content of these protected memory blocks is ignored. These protected memory blocks are listed in the following tables.

Table 8. Write Protection Area IF WPS = 0 and CMP Bit = 0Protected Area Sizes (WPS = 0, CMP Bit = 0)
Status Bit					Memory Content				Portion
BP4	BP3	BP2	BP1	BP0	Blocks	Addresses		Density
BP4	BP3	BP2	BP1	BP0	Blocks	Start	End	Density
x	x	0	0	0	–	–	–	–	–
0	0	0	0	1	31	1F0000	1FFFFF	64 KB	Upper 1/32
0	0	0	1	0	30 – 31	1E0000	1FFFFF	128 KB	Upper 1/16
0	0	0	1	1	28 – 31	1C0000	1FFFFF	256 KB	Upper 1/8
0	0	1	0	0	24 – 31	180000	1FFFFF	512 KB	Upper 1/4
0	0	1	0	1	16 – 31	100000	1FFFFF	1 MB	Upper 1/2
0	1	0	0	1	0	000000	00FFFF	64 KB	Lower 1/32
0	1	0	1	0	0 – 1	000000	01FFFF	128 KB	Lower 1/16
0	1	0	1	1	0 – 3	000000	03FFFF	256 KB	Lower 1/8
0	1	1	0	0	0 – 7	000000	07FFFF	512 KB	Lower 1/4
0	1	1	0	1	0 – 15	000000	0FFFFF	1 MB	Lower 1/2
x	x	1	1	x	0 – 31	000000	1FFFFF	2 MB	All
1	0	0	1	1	31	1FF000	1FFFFF	4 KB	Upper 1/512
1	0	1	0	0	31	1FE000	1FFFFF	8 KB	Upper 1/256
1	0	1	0	1	31	1FC000	1FFFFF	16 KB	Upper 1/128
1	0	1	0	x	31	1F8000	1FFFFF	32 KB	Upper 1/64
1	1	0	1	1	0	000000	000FFF	4 KB	Lower 1/512
1	1	1	0	0	0	000000	001FFF	8 KB	Lower 1/256
1	1	1	0	1	0	000000	003FFF	16 KB	Lower 1/128
1	1	1	0	x	0	000000	007FFF	32 KB	Lower 1/64

Table 9. Write Protection Area IF WPS = 0 and CMP Bit = 1Protected Area Sizes (WPS = 0, CMP Bit = 1)
Status Bit					Memory Content				Portion
BP4	BP3	BP2	BP1	BP0	Blocks	Addresses		Density
BP4	BP3	BP2	BP1	BP0	Blocks	Start	End	Density
x	x	0	0	0	0 – 31	0	1FFFFF	2 MB	All
0	0	0	0	1	0 – 30	000000	1EFFFF	1984 KB	Lower 31/31
0	0	0	1	0	0 – 29	000000	1DFFFF	1920 KB	Lower 15/16
0	0	0	1	1	0 – 27	000000	1BFFFF	1792 KB	Lower 7/8
0	0	1	0	0	0 – 23	000000	17FFFF	1536 KB	Lower 3/4
0	0	1	0	1	0 – 15	000000	0FFFFF	1 MB	Lower 1/2
0	1	0	0	1	1 – 31	010000	1FEFFF	1984 KB	Upper 31/31
0	1	0	1	0	2 – 31	020000	1FEFFF	1920 KB	Upper 15/16
0	1	0	1	1	4 – 31	0400000	1FEFFF	1792 KB	Upper 7/8
0	1	1	0	0	8 – 31	080000	1FEFFF	1536 KB	Upper 3/4
0	1	1	0	1	16 – 31	100000	1FEFFF	1 MB	Upper 1/2
x	x	1	1	x	–	–	–	–	–
1	0	0	0	1	0 – 31	000000	1FEFFF	2044 KB	Lower 511/512
1	0	0	1	0	0 – 31	000000	1FDFFF	2040 KB	Lower 255/256
1	0	0	1	1	0 – 31	000000	1FBFFF	2032 KB	Lower 127/128
1	0	1	0	x	0 – 31	000000	1F7FFF	2016 KB	Lower 63/64
1	1	0	0	1	0 – 31	001000	1FFFFF	2044 KB	Upper 511/512
1	1	0	1	0	0 – 31	002000	1FFFFF	2040 KB	Upper 255/256
1	1	0	1	1	0 – 31	004000	1FFFFF	2032 KB	Upper 127/128
1	1	1	0	x	0 – 31	008000	1FFFFF	2016 KB	Upper 63/64

If WPS = 1, individual block/sector protection is enabled. All individual block/sector lock bits are set to 1 by default after power up, meaning that the entire memory array is protected. The following table shows the protected block/sector areas of the memory. To write to or erase the content of any of these protected block/sector areas of memor, either a command must be given to unlock an individual memory block at a specified address, or a Global Block Unlock command must be issued.

Table 10. Individual Block Protection (WPS=1)
Blocks	Memory Content				Block/Sector Lock Commands
	Sector	Addresses		Density
	Sector	Start	End	Density
0	0	000000	000FFF	4 KB	36h, 39h, 3Dh
	1	001000	001FFF	4 KB	36h, 39h, 3Dh
	-	-	-	-	-
	14	00E000	00EFFF	4 KB	36h, 39h, 3Dh
	15	00F000	00FFFF	4 KB	36h, 39h, 3Dh
1	All	010000	01FFFF	64 KB	36h, 39h, 3Dh
2	All	020000	02FFFF	64 KB	36h, 39h, 3Dh
3	All	030000	03FFFF	64 KB	36h, 39h, 3Dh
-	-	-	-	-	-
28	All	1C0000	1CFFFF	64 KB	36h, 39h, 3Dh
29	All	1C0000	1CFFFF	64 KB	36h, 39h, 3Dh
30	All	1E0000	1EFFFF	64 KB	36h, 39h, 3Dh
31	496 (0)	1F0000	1F0FFF	4 KB	36h, 39h, 3Dh
	497 (1)	1F1000	1F1FFF	4 KB	36h, 39h, 3Dh
	-	-	-	-	-
	510 (14)	1FE000	1FEFFF	4 KB	36h, 39h, 3Dh
	511 (15)	1FF000	1FFFFF	4 KB	36h, 39h, 3Dh
0 – 31	All	000000	1FFFFF	2 MB	7Eh, 98h

Revision History

Table 11. Revision History
Date	Version	Description
???	1.1	PENDING (DOC-2897)
April 2025	1.0	Initial release.