Calibrating with Dynamic Delay (/ only)

On and s, LVDS RX supports dynamic delay mode. The dynamic delay can be applied to both clock and data lanes by enabling the Dynamic Mode Delay Settings in the Interface Designer. Additional control signals are made available for tuning the delay value in user core logic.

A parallel clock (slowclk) from PLL is required to supply the dynamic delay control block. LVDS Dynamic Delay block is pll_slowclk positive edge triggered. The following requirments must be satisfied to assert the signals for the dynamic delay control block:
  • Assert RX_DLY_RST on the positive edge of pll_slowclk
  • Assert RX_DLY_INC and RX_DLY_ENA on negative edge of pll_slowclk
Table 1. LVDS Dynamic Delay Block Assertion Requirements
Dynamic Delay Control Signals Signal Assertion Description
RX_DLY_RST Positive edge of pll_slowclk Active HIGH reset. Reset the delay step count to 31.
RX_DLY_ENA Negative edge of pll_slowclk Active HIGH delay enable.
0: Same as previous delay step count.
1: Enable to increase/decrease delay step count.
RX_DLY_INC Negative edge of pll_slowclk 0: Decrease delay step count every clock cycle.
1: Increase delay step count every clock cycle.
Each lane offers 64 taps (value 0–63), with each tap adding approximately 20 ps of delay. The reset signal (RX_DLY_RST) resets the delay count to half of the maximum count value – step 31. The updated delay takes effect approximately 5 ns after the rising edge of the parallel clock.
Figure 1. Example Dynamic Delay Control Waveform