RX Edge-Aligned

For the LVDS RX clock lane, set the connection type to pll_clkin.

The following clocks from a single PLL source must be provided to the LVDS RX interface to receive center-aligned signals:
  • pll_slowclk—Parallel clock LVDS RX blocks, data lanes
  • pll_fastclk—Serial clock for LVDS RX blocks, data lanes
The frequency, phase, pll_slowclk, and pll_fastclk PLL settings are as follows:
Table 1. Requirements for Frequency and Phase
Frequency Phase
slowclk rx_refclk frequency 0
fastclk Half-Rate:
slowclk frequency × (deserialization width ÷ 2)
Full-Rate:
slowclk frequency × deserialization width
 Half-Rate: 90º
Full-Rate: 180º
feedbackclk (core feedback) rx_refclk frequency 360 ÷ (2 × serialization width)
Figure 1. / RX, Half-Rate, Edge-Aligned Waveform. Deserialization: 1-to-8
Figure 2. / RX, Full-Rate, Edge-Aligned Waveform. Deserialization: 1-to-8