AN 046: Reset Guidelines for Efinix FPGAs

The reset signal can drive the flipflop SR port directly. However, the Efinity® software can also use additional resources so that the set/reset signal feeds the D input port instead of the SR port for more flexibility. To allow Efinity software to implement this feature, set the --infer-sync-set-reset synthesis option to 0 (disable) in the Project Editor's Synthesis tab.

The following figure shows the example of an additional logic implementation where the reset signal is connected to the D input port through an additional logic.

If you use a PLL to clock the flipflops, the flipflops must be held in reset until the PLL is locked and the clock output is stable. You can use the PLL locked signal to gate the reset signal feeding the flipflops. Add a counter to hold the registers in reset even after configuration is done until t_USER has elapsed. The counter also acts as a reset synchronizer, ensuring the reset de-assertion is synchronous to the PLL clock output.

You need to calculate the number of PLL output clock cycles required to ensure the reset signal is de-asserted after t_USER elapsed. The following example calculates the required number of PLL output clock cycles for a Titanium FPGA (t_USER = 25 μs) with a PLL output clock frequency of 50 MHz.

Clock cycles required = t_USER/ PLL output clock period = 25 μs / (1/50 MHz) = 1,250

The counter should hold the reset for at least 1,250 clock cycles.

always@(posedge clkout, negedge rst_n)
begin 
   if (!rst_n)
   begin
      rst_n_sync <= 1'b0;
      counter <= 11'b0;
   end
   else
   begin 
      if (counter < 1250)
         counter <= counter + 1'b1;
      else
         rst_n_sync <= 1'b1;
   end
end

process (clk, rst_n)
begin
   if rst_n = '0' then 
      rst_n_sync <= '0';
      counter <= (others => '0');
   elsif rising_edge(clk) then
      if (counter <1250) then
         counter <= counter + 1; 
      else
         rst_n_sync <= '1';
      end if;
   end if;
end process;

There may be times when the PLL loses lock, or the reset_n signal is triggered while the FPGA is in user mode. In these situations, the reset counter restarts the count on the number of cycles to wait before releasing the registers from reset. The counter starts after the PLL regains lock or the reset_n signal is de-asserted.

You can use a counter to generate a reset signal to hold your design in reset after configuration has completed and automatically releases the design after t_USER has elapsed.

You can also use an output pin to generate a signal that indicates when the device goes into the user mode. This signal can be used as a reset signal to your design.

You can use the reset signal to initialize the flipflops in your design. The following code example shows how resetting the design also sets the flipflop to a logic 1 before starting an operation.

always@(posedge clk)
begin 
    if (!rst_n)
        q_out <= 1'b1;
    else
         q_out <= d_in;
end

process (clk)
begin
    if rising_edge(clk) then
        if rst_n = '0' then 
            q_out <= '1';
        else 
            q_out <= d_in;
        end if;
    end if;
end process;

Typically, you initialize flipflops with RTL codes for simulation but it is also synthesizable by the Efinity software. The Efinity software implements additional logic during synthesis to ensure the output is initialized to the desired value. The following figure and example codes show the implementation result with additional logic to initialize the output to logic 1.

reg q_out = 1'b1;
always@(posedge clk)
begin 
    if (!rst_n)
        q_out <= 1'b0;
    else
         q_out <= d_in;
end

initial 
begin 
    q_out <= 1'b1;
end

always@(posedge clk)
begin 
    if (!rst_n)
        q_out <= 1'b0;
    else
         q_out <= d_in;
end

signal q_out: STD_LOGIC := '1';
…
    process (clk)
    begin
        if rising_edge(clk) then
            if rst_n = '0' then 
                q_out <= '0';
            else
                q_out <= d_in;
            end if;
        end if;
    end process;

The EFX_SRL8 primitive in Titanium FPGAs allows you to implement an 8-bit shift register function in XLR cells. The 8-bit shift register content can be initialized with the EFX_SRL8 primitive, so the reset is not required for content initialization.

Additional logic is required if you implement the 8-bit shift register function in the XLR cell through your own RTL code.

The Titanium FPGA memory blocks support asynchronous and synchronous reset of the RAM output, and asynchronous reset of the RAM output register. The RAM output and RAM output register reset share the same reset input port but can be enabled independently. The embedded memory block in the true-dual-port mode has two reset ports, one for port A and the other for port B. Asserting the reset signal does not clear the RAM content.

You can initialize the memory block content for Trion and Titanium FPGAs when instantiating through the primitives.

The Titanium DSP blocks include a reset port that supports synchronous and asynchronous reset. This reset port can drive the reset for registers A, B, C, OP, P, W, and O. You can enable or disable the reset for each register independently. You can enable the synchronous reset and reset the registers together with other sequential logic in your design using the system reset when the FPGA goes into user mode.

The Trion multiplier blocks include reset ports to set or reset registers A, B, and O. The registers support synchronous and asynchronous reset or set. You can enable the synchronous reset and reset the registers together with other sequential logic in your design through the system reset when the FPGA goes into user mode.