AN 063: High-Speed Transceiver Design Guidelines

Introduction

Titanium™ and Topaz™ transceivers consist of a physical medium attachment (PMA) and a physical coding sublayer (PCS). The PMA connects the FPGA to the lane, generates the required clocks, and converts the data from parallel to serial or serial to parallel. The PCS contains the digital processing interface between the PMA and the FPGA fabric. The PCS supports SGMII, 10GBase-KR, and up to PCIe® Gen4, as well as PMA Direct.

The transceivers support up to Gen4 x4, which is equivalent to a 16 Gbps lane rate or up to 64 Gbps link bandwidth. Therefore, proper hardware design is essential to ensure reliable high-speed data transmission. These guidelines provide comprehensive guidance regarding schematic-level design considerations and PCB layout guidelines for high-speed transceivers under different modes of operation.

Circuit Design Considerations

Several schematic-level design factors need to be considered when designing your board. These factors include:
  • PMA Direct
  • 10GBase-R/KR
  • PCIe Interface
  • Pre-emphasis, de-emphasis, and equalization

PMA Direct

The following graph shows the maximum RX channel insertion loss allowed by data rate for the PMA Direct PHY in 20-bit or 40-bit data widths.

Figure 1. 20b PHY RX Channel Loss vs. Data Rate

The maximum permitted channel insertion loss for RX operating in 32-bit or 64-bit data width modes is 25 dB across different data rates. For long-reach applications operating at higher bit rates, Efinix recommends using either 32-bit or 64-bit data width modes.

At 6.25 GHz (for 12.5 Gbps data rate), the insertion loss estimates below are based on the PCB material:
  • M6: ~0.5 dB/inch
  • FR4: ~1 dB/inch
Figure 2. HCSL REFCLK Input Reference

Figure 3. LVDS REFCLK Input Reference

The PMA Direct PHY has the following AC coupling requirements. The PMA Direct REFCLK pin supports HCSL or LVDS differential clock signals. Use an external biasing circuit to keep the signal amplitude within the valid range. Consult the device data sheet for detailed REFCLK specifications. Do not drive current into the HCSL REFCLK input pins before entering user mode. If you cannot hold the external clock during CRESET_N, disable the internal termination and apply a 50 Ω external resistor.

Figure 4. External RX Path

10GBase-R/KR

Local Area Networks (LANs) conforming to the IEEE 802.3-2012 Ethernet Standard rely on optical modules, routers, and servers corresponding to the 10GBase-R standard. The electrical backplane, on the other hand, comprises a transmission medium corresponding to the 10GBase-KR standard.

The physical 10GBase-R/KR layer includes the Physical Medium Dependent (PMD), PMA, and PCS, which respectively comprise the physical connection, receive equalization/transmit equalization, receive clock recovery, parallel signal serialization/high-speed serial signal deserialization, and 64b/66b encoding and decoding. Because 10G uses 64b/66b encoding, the actual rate at which 10 Gbps data is transmitted over the medium after encoding is 10.3125 Gbps (i.e., 10 Gbps × 66 ÷ 64 = 10.3125 Gbps).

Therefore, the 10GBase-R/KR interface operates at a clock frequency of: 10312.5 ÷ 66 = 156.25 MHz.

10G SFP+ Interface

The 10G Enhanced Small Form-factor Pluggable (SFP+) optical module is a hot-swappable optical transceiver. It is commonly used in 10 Gbps applications, such as SONET/SDH, Fiber Channel, and 10 Gigabit Ethernet. For Titanium and Topaz boards, when configured as 10GBase-R in KR mode, the high-speed transceiver interface can work with an external 10G SFP+ optical module. An example connection can be found on the Titanium Ti375 N1156 Development Board.

Because the 10G SFP+ interface is widely used, the following section uses the 10G SFP+ interface as an example to introduce the 10G transceiver interface design.

The SFP+ interface is mainly divided into two parts: host and module. The host is part of the SFP+ optical module interface. The module itself does not consist of CDR circuits. Therefore, dimension and power consumption can be minimized.

The electrical interface connecting the FPGA transceiver interface on the host side and the SFP+ optical module is referred to as a SerDes Framer Interface (SFI). This SFI electrical interface is based on high-speed, low-voltage AC coupling logic. The nominal differential impedance is 100 Ω, as shown in the following figure.

Figure 5. SFP+ Interface Block Diagram

10G SFP+ Interface Pinout Description

The following figure is a schematic diagram of the SFP+ interface signal on the host side, which corresponds to the 20-pin optical interface connector.

Figure 6. Host PCB SFP+ Pin Assignment

The following figure shows the pins on the side of the SFP+ optical module, which corresponds to the edge card connector of the optical module.

Figure 7. SFP+ Module Pin Assignment

The following table describes the pin assignment of the SFP+ interface:

Table 1. SFP+ Module and Host Electrical Contact Definition
Pin # Signal Name Logic Level Description
1 VeeT Module Transmitter Ground.
2 TX_Fault LVTTL-O Module Transmitter Fault.
Open-drain output, which needs to be pulled up to VCC on the host side to indicate an error in the SFP+ module sending.
3 TX_Disable LVTTL-I Transmitter Disable. Turns off transmitter laser output. Required connection to FPGA for transmission permission control.
4 SDA LVTTL-I/O Two-Wire Serial Interface Data Line. Pull-up resistor required.1
5 SCL LVTTL-I/O Two-Wire Serial Interface Clock. Pull-up resistor required.1
6 Mod_ABS Module Absent, connected to VeeT or VeeR in the module.
7 RS0 LVTTL-I Rate Select 0, optionally controls SFP+ module receiver. Connects to FPGA.2
8 RX_LOS LVTTL-O Receiver Loss of Signal Indication (designated as RX_LOS in FC and Signal Detect in Ethernet).
Open-drain output, which needs to be pulled up to VCC on the host side to instruct the SFP+ module to receive LOS alarms. RX_LOS needs to be connected to the FPGA. If the system needs to select a clock source, the LOS alarm will be monitored.
9 RS1 LVTTL-I Rate Select 1, optionally controls SFP+ module receiver. Connects to FPGA.2
10 VeeR Module Receiver Ground.
11 VeeR Module Receiver Ground.
12 RD- CML-O Receiver Inverted Data Output.
13 RD+ CML-O Receiver Non-Inverted Data Output.
14 VeeR Module Receiver Ground.
15 VccR Module Receiver 3.3 V Supply.3
16 VccT Module Transmitter 3.3 V Supply.3
17 VeeT Module Transmitter Ground.
18 TD+ CML-I Transmitter Non-Inverted Data Input.
19 TD- CML-I Transmitter Inverted Data Input.
20 VeeT Module Transmitter Ground.

Differential Signals

The signal pair is LVDS, which requires AC coupling. The SFP+ module has integrated AC coupling capacitors. The 100 Ω termination resistor can be configured inside the FPGA. Therefore, the transceiver's differential signal for the SFP+ interface is connected directly to the differential interface of the FPGA.

The following figure shows the transceiver interface connection of the SFP+ optical module.

Figure 8. SFP+ Interface Termination and AC Coupling

Reference Clocks

Per Figure 5, there are only two pairs of differential signals between the SFP+ optical module and the FPGA’s transceiver interface. Nevertheless, the transceiver interface of the FPGA requires a reference clock for normal operation. For reference clock requirements and recommendations, see PMA Direct.

In 10G Base-R/KR mode, the reference clock frequency is 156.25 MHz. In SGMII mode, the reference clock frequency is 125 MHz.

The following table lists the typical electrical characteristics required of a 10G SFP+ interface reference clock.

Table 2. Reference Clock Typical Requirements for SFP+ Interface
Requirements Condition Minimum Typical Maximum Unit
Reference Clock Frequency 156.25 MHz
Frequency Stability <25 ppm
Jitter <200 fs
Rise Time 20% ~ 80% - 200 - Ps
Drop Time 80% ~ 20% - 200 - Ps
Duty Cycle Requirements 40 50 60 %
Vpk-pk Voltage 250 - 2,000 mV
Differential Input Impedance - 100 - Ω

PCIe Interface

PCIe v4.0 offers greater flexibility and bandwidth over its v3.0 predecessor, with a maximum transfer rate of 16 GT/s. The following table outlines the line code and maximum transfer rate for each PCIe generation.

Table 3. PCIe Generation Comparison
Generation Line code Max. Transfer Rate (per lane)
1.0 NRZ 8b/10b 2.5 GT/s
2.0 5.0 GT/s
3.0 128b/130b 8.0 GT/s
4.0 16.0 GT/s

Pin Definition

Table 4. PCIe x4 Connector Pinout
Pin # Side B Side A
Name Description Name Description
1 +12 V +12 V power PRSNT1# Hot-plug presence detected
2 +12 V +12 V power +12 V +12 V power
3 +12 V +12 V power +12 V +12 V power
4 GND Ground GND Ground
5 SMNCLK SMBus (System Management Bus) clock JTAG2 TCK
Clock input for JTAG interface
6 SMBDAT SMBus (System Management Bus) data JTAG3 TDI
7 GND Ground JTAG4 TDO
8 +3.3 V +3.3 V power JTAG5 TMS
9 JTAG1 TRST# (Test Reset)
Resets the JTAG interface.
 +3.3 V +3.3 V power
10 +3.3 Vaux +3.3 V auxillary power +3.3 V +3.3 V power
11 WAKE# Signal for link reactivation PERST# Fundamental reset
Mechanical Key
12 CLKREQ# Clock Request Signal GND Ground
13 GND Ground REFCLK+ Reference clock (differential pair)
14 PETp0 Transmitter differential pair, lane 0 REFCLK–
15 PETn0 Transmitter differential pair, lane 0 GND Ground
16 GND Ground PERp0 Receiver differential pair, lane 0
17 PRSNT2# Hot-plug presence detected PERn0
18 GND Ground GND Ground
End of the x1 Connector
19 PETp1 Transmitter differential pair, lane 1 RSVD
20 PETn1 GND Ground
21 GND Ground PERp1 Receiver differential pair, lane 1
22 GND Ground PERn1
23 PETp2 Transmitter differential pair, lane 2 GND Ground

PCIe Reference Clocks

The two main types of clock architecture in PCIe systems are common and separate reference clocks.

Figure 9. PCIe Clock Architecture

As the name suggests, in a common clock architecture the PCIe devices share the same PLL clock. This method is the most widely used clock architecture in PCIe systems. For PCIe Gen4 or below, the required frequency stability is ±300 ppm.

The separate clock architecture use different clock sources for the host and endpoint devices. The frequency stability requirement is ±100 ppm regardless of the system's bit rate. Both common and separate clock architectures support spread spectrum clocking (SSC) for reducing electromagnetic interference.

The jitter limit, shown in the following table, is specified according to PCIe generation.

Table 5. REFCLK Jitter Limit Requirements
PCIe Generation REFCLK Phase Jitter Limit (ps RMS)
PCIe 1.1 86
PCIe 2.1 3.1
PCIe 3.1 1.0
PCIe 4.0 0.5
Additional AC and DC requirements for PCIe REFCLK are as shown in the following table:
Table 6. REFCLK Timing Requirements
Symbol Parameter 100 MHz Input Units
Min. Max.
Rising Edge Rate Rising Edge Rate 56 0.6 4.0 V/ns
Falling Edge Rate Falling Edge Rate56 0.6 4.0 V/ns
VIH Differential Input High Volatage5 +150 mV
VIL Differential Input Low Volatage5 –150 mV
VCROSS Absolute Crossing Point Voltage4 +250 +550 mV
VCROSS DELTA Variation of VCROSS Over All Rising Clock Edges4 +140 mV
VRB Ring-Back Voltage Margin5 –100 +100 mV
TSTABLE Time Before VRB is Allowed5 500 ps
TPERIOD AVG Average Clock Period Accuracy5 –300 +2800 ppm
TPERIOD ABS Absolute Period (including Jitter and Spread Spectrum Modulation)5 9.847 10.203 ns
TCCJITTER Cycle to Cycle Jitter5 150 ps
VMAX Absolute Maximum Input Voltage4 +1.15 V
VMIN Absolute Minimum Input Voltage4 –0.3 V
Duty Cycle Duty Cycle5 40 60 %
Rise-Fall Matching Rising Edge Rate (REFCLK+) to Falling Edge Rate (REFCLK–) Matching4 20 %
ZC-DC Clock Source DC Impedance4 40 60 Ω
The PCIe Controller accepts clock signals from both REFCLK0_P/N and REFCLK1_P/N.
Note: For computer applications, the main board has a reference clock for add-in cards on pin 13-14 on side A. The REFCLK is a 100-MHz HCSL clock.
Figure 10. PCIe Reference Clock Termination
Note: The default clock reference is REFCLK0. The clock multiplexer requires some clock toggling to switch from REFCLK0 to REFCLK1. For more details, please refer to the Titanium PCIe® Controller User Guide.

For the reference clock measurement method, refer to the requirements in the following waveform diagrams:

Figure 11. Rise/Fall Edge for Differential Reference Clock

Figure 12. Rise/Fall Edge for Signal-Ended Reference Clock

Figure 13. Period and Duty Cycle for PCIe Reference Clock

Figure 14. Ring Requirements for PCIe Reference Clock

Reset Signals (PERST_N)

The reset signal is used by the host device to indicate that the device power and reference clock are stable, and that link initialization is ready to begin. In Titanium and Topaz devices, the PERST pin must connect to a dedicated pin, such as PERST_Q0_N or PERST_Q2_N, for proper operation.

Implementing a Hot-Plug PCIe Interface

To implement the hot-plug features on PCIe add-in cards requires the mechanical support of the PRSNT1# and PRSNT2# pin connectors. These are the first and the most distant pins on the add-in card.
Note: For a x4 add-in card, PRSNT1# and PRSNT2# are mapped on A1 and B31, respectively.
On the PCB footprint, these are the shortest pins on the edge connector and the last signal connection during card insertion.

On the host board, if presence detection is supported, PRSNT1# must connect to ground and PRSNT2# must connect with a pull-up resistor; otherwise, both must be left unconnected. The following diagram illustrates hot-plug implementation.

Figure 15. PCIe Hot Plug

PCIe Interface Differential Signals

According to the PCIe specification, the:
  • PCIe interface differential signal uses AC coupling mode
  • AC coupling capacitor is located on the TX side
  • Capacitance size is 176 nF~265 nF
  • Conventional selection is 220 nF
  • Recommended package is 0201
Figure 16. Differential Signal Connection for PCIe Interface

Power Up Sequence

The PCIe endpoint device must follow the power-up sequence as described in the Titanium PCIe® Controller User Guide.

Figure 17. Power-Up Sequence
Boot-Up Timing Requirements

According to the PCIe specifications, the endpoint device must ensure that the board completes boot-up within 100 ms after PERST# deasserted. Therefore, it is necessary to take into consideration the following design concerns:

  • Overall power-rail start-up timing.
  • SPI, data width and data rate, configuration time.
  • Using PLL BL0 or BR0 for quad with an on-board oscillator as the PLL input clock source (depending on whether you are using quad 0 or quad1).

For more information, refer to the Titanium PCIe® Controller User Guide.

Power-Down Sequence

The correct power-down sequence for the PCIe interface is as follows:

  1. Before unplugging the AIC, the system must put the PCIe link into an inactive state.
  2. The host asserts PERST#.
  3. The system inactivates REFCLK and JTAG.

The following waveform illustrates the power down process.

Figure 18. Power-Down Sequence

Pre-Emphasis, De-Emphasis, and Equalization

During signal transmission, different frequency components experience varying degrees of attenuation leading to distortion in the received signal. To achieve a better waveform at the receiving end, it is essential to compensate for signal degradation. Common compensation techniques include pre-emphasis, de-emphasis, and equalization.

In high-speed signal transmission, high-frequency components are attenuated significantly more than low-frequency components, thus causing the transmission line to behave like a low-pass filter.

Pre-Emphasis

Pre-emphasis involves boosting the signal's high-frequency components at the start of the transmission line to counteract the excessive attenuation they face during transmission. These high-frequency components are primarily found at the rising and falling edges of the signal. The pre-emphasis technique enhances the amplitude at these edges.

De-Emphasis

The goal is to maintain a constant amplitude at the rising and falling edges while reducing the amplitude of the signal elsewhere. This approach offers several advantages, such as lower power consumption and reduced electromagnetic interference (EMI).

Equalization

Equalization techniques can effectively address signal loss during transmission and improve overall signal quality. However, both pre-emphasis and de-emphasis techniques have their limitations; for example, they can inadvertently amplify high-frequency crosstalk, thereby exacerbating its impact. Equalization helps to mitigate these drawbacks. This technique functions as a high-pass filter, compensating for distorted pulses. An adaptive equalizer continuously adjusts its gain based on the actual digital signal transmitted, using an algorithm to respond to random channel changes. This adaptability ensures that the equalizer remains optimally configured, enhancing its ability to compensate for distortion.

PCB Design Considerations

Several factors need to be considered in the design of your board. These factors include:
  • Board material selection
  • PCB stack up
  • Impredance control
  • Routing guidelines

Board Material Selection

In high-frequency applications, the choice of board material is essential for ensuring optimal signal integrity, thermal management, and overall reliability. Materials with low dielectric constants and dissipation factors, high thermal stability, and good mechanical properties are essential for maintaining performance in high-speed electronic systems. Selecting the right material minimizes losses and enhances the efficiency of the circuit, thus making it a critical consideration in PCB design.

Dielectric Constant (Dk)

The dielectric constant (Dk), or relative permittivity, is a measure of a material's ability to store electrical energy in an electric field relative to the vacuum. Dk is a critical property in the design and performance of electronic circuits, particularly in high-frequency applications, such as RF and microwave circuits. A lower Dk value (less than 4) is preferred as it helps reduce signal loss and maintain signal integrity. Medium Dk materials (around 4 to 10) offer a balance between cost and performance.

Dissipation Factor (Df)

The dissipation factor (Df), also known as the loss tangent (δ), is a measure of how much energy from an electric field is lost as heat in a dielectric material. Df is a critical parameter in determining the efficiency and performance of electronic components, particularly in high-frequency applications. A low Df (less than 0.005) is essential for minimizing energy loss and heat generation, an is especially important in high-frequency scenarios. A medium Df (around 0.005 to 0.02) offers a balance between cost and performance.

Thermal Stability (Tg)

The Glass Transition Temperature (Tg) represents the temperature threshold at which resin transforms from a solid state to rubbery fluid. High-frequency circuits can generate significant heat. Materials with high Tg can better withstand thermal cycling and maintain their properties, ensuring reliable operation over time. Tg is one of the important characteristics of PCB substrates, and is classified as:

  • General Tg sheet: 130℃-150℃, such as KB-6164F (140℃), S1141 (140℃)
  • Medium Tg sheet: 150℃-170℃, such as KB-6165F (150℃), S1141 150 (150℃)
  • High Tg sheet: 170℃ and above, such as KB-6167F (170℃), S1170 (170℃)

Other Considerations

Other PCB material properties, such as Conductive Anodic Filament (CAF), Thermal Conductivity (TC), Coefficient of Thermal Expansion (CTE), etc., must be considered in terms of the manufacturing of high-density, high-power applications.

Table 7. Examples of PCB Materials
Type Dk (1GHz) Df (1GHz) Price Reference
Resin 3.6 0.025 Low TU768/TU752/IT180A
PPE 2.45 0.007 High Megtron6/TU883
PTPE 2.1 0.0004 Very high RO3000 Series

PCB Stack Up

Due to the growth in the demand for more compact PCBs, the issue of design stack up has become increasingly important. Good PCB management also helps reduce EMI and improve signal integrity. Here are some rules for stack-up design:

  • If the high-speed signal goes through the surface layer, the adjacent layer needs a complete ground plane.
  • If the high-speed signal goes to the inner layer, the upper/lower adjacent layers should be placed with a complete ground plane.
  • The power plane must be adjacent to the full ground plane layer and tightly coupled.
  • TX and RX signals for high-speed differential signals should ideally be placed in different layers.
  • From the perspective of EMC, a high-speed clock and high-speed parallel signal avoids surface wiring.
  • Stackups need to be cost-effective.

According to the PCIe CEM specifications, the overall thickness of a PCIe card should be 1.57 mm.

Impedance Control

Target trace impedance for PCIe interfaces should follow the recommendations below. The tolerance for manufacturing should be kept at ±5%.

PCIe Generation Single-End Impedance
(Units = Ω)
 Differential Impedance
(Units = Ω)
Gen1 50 100
Gen2 50 100
Gen3 50 or 42.5 100 or 85
Gen4 42.5 85

Routing Guidelines

In the course of designing your PCB, you must observe the following routing guidelines:

Microstrip vs Stripline

Microstrip traces are located on the surface layers while stripline is fully confined, meaning that it has minimal radiation and resistance to interference. There are no strict rules regarding which way the high-speed signals need to be routed. Engineering should make the determination between microstrip and stripline routine according the use case scenario. The following topics compare the advantages and disadvantages of microstrip vs stripline.

Microstrip
  • Consists of a signal conductor strip and references to the adjacent ground plane with a layer of dielectric separation.
  • Structure is simple, cost effective, and does not incur vias if interlayer routing is avoided. This strategy reduces the parasitic capacitance and inductance from via structure in high frequency applications. It also avoids signal reflection caused by via stubs.
  • Reference plane is one-sided if the dielectric constant is less than the stripline, meaning that the transmission line delay is smaller and achievable for higher speed propagation.
  • Microstrips are subject more interference as they are located on the surface layers.
Stripline
  • Consists of an inner signal conductor strip sandwiched between two parallel reference planes (normally ground planes). These shield the signal and provide good EMC protection. However, fabrication complexity increases with the number of stack-up layers.
  • Vias are required when traces change layers from top/bottom to inner. Through-hole vias introduce via stubs, which can be a source of signal reflection. Using blind or buried vias, or back drilling, can eliminate this issue, but increases production costs.

High-Speed Differential Trace Recommendations

The following recommendations are provided to ensure the quality of high-speed differential traces.

Trace Length

The trace length budget for add-in cards is a maximum of 101.6 mm, and with a maximum width of approximately 0.127 mm. Differential pairs are required to maintain equal width throughout the board.

Spacing

The spacing between P and N wires of the differential pairs is determined by the design impedance according to line width, copper thickness, PCB material, and lamination. The spacing should be kept constant throughout, from the main chip to the edge connector. For example, if the clock signal width is x1, the distance between the clock signal and other signals should be consistent at x5 spacing.

Skew Matching

The intra-pair skew requirement for high-speed differential pairs is <0.127 mm. There are no inter-pair skew requirements in the PCIe specification.

Bending

Round bending is recommended to maintain the continuity of impedance; however, 45° corners are acceptable. Do not use right-angle bends.

Other Routing Recommendations

Place TX and RX signals in different layers. Differential signal routing must be kept away from crystal oscillators, DC modules, magnetic components, and so on.

PCIe v4.0 Routing Guide

In addition to the common routing requirements for differential signals, it is also necessary to comply with the following PCIe v4.0 specifications:

PCIe v4.0 Edge Card Connector Reference Plane

Per the PCIe v4.0 specifications, there is no inner conductor within 381 microns below the edge card connector, including no ground plane or power plane. It is recommended that the inner layer be more than 381 microns, and the ground plane placed to prevent crosstalk between TX and RX. Refer to the following diagram for details:

Figure 19. PCIe v4.0 Edge Card Connector Reference Plane Schematic
PCIe Edge Card Connector Length

The length of the edge card connector is 3.91 mm, and the entire length (including the chamfer area) of the edge card connector is 5.6 mm. The space between the edge card connector area and the chamfer area is 0.39 mm, which is less than in Gen 1.

A small amount of residual surface metal is allowed within the 0.13 mm area beyond the lower end of the edge card connector.

The PRSNT1# or PRSNT2# pins should be 3.2 mm in length, while the non-functional PRSNT2# edge card connector can be either 3.2 mm or 3.91 mm long.

Figure 20. PCIe v4.0 Edge Card Connector Reference Plane Schematic
Ground Hole Requirements

The ground hole of the edge card connector must be distributed in the middle of the adjacent pins of the edge card connector so as to reduce the interference of the signal outlet. From the top edge of the edge card connector to the bottom edge of the ground vias should not exceed 127 microns. The width of the traces connected to the ground via and ground pin must be greater than or equal to the diameter of the via pad to minimize ground inductance. The front and back ground pins of edge card connector can share ground vias.

Figure 21. PCIE 4.0 Edge Card Connector Via Requirements
Merging Edge Card Connector Ground Vias

Edge card connector ground pins are adjacent to each other, with the ground vias connected to the ground pin connected together. The ground holes can also be shared on both sides.

Revision History

Date Version Description
March 2026 1.3 Add LVDS and HSCL RefClk recommended circuitry to PMA Direct. (DOC-2931)
Fix various typos.
February 2026 1.2 Updated PMA Direct with AC coupling requirements. (DOC-2871)
July 2025 1.1 Updated PMA Direct with RX insertion loss guidelines. (DOC-2619)
March 2025 1.0 Initial Release.
1 Some SFP+ modules support reading the temperature of the optical module, which is useful when the optical interface power is relatively high. If there are multiple optical modules present, but the FPGA only has one set of I2C interfaces available, adding I2C buffer applies to ensure the reliability of I2C access.
2 If RS0 and RS1 select GE modules, then the signal format of the SFP+ interface is SGMII. In this case, the FPGA's transceiver interface reference clock should be adjusted from 156.25 MHZ of 10 G to 125 MHZ of GE.
3 Ferrite beads and a capacitor filter are recommended for supply noise reduction.
4 The measurement spec is for the waveform of a single-ended signal.
5 The measurement spec is for the waveform of the differential signal.
6 Regarding the frequency stability of the reference clock, the clock accuracy requirements are different depending on the clock architecture.