Resets

The Sapphire SoC has as master reset signal, io_asyncReset that triggers a system reset. Your RTL design should hold io_asyncReset for 10 ns to reset the whole SoC system completely. When you assert io_asyncReset, the SoC asserts:
  • io_systemReset, which resets the RISC-V processor, on-chip memory, and peripherals.
  • io_peripheralReset, which resets the APB3 peripherals and AXI4 master.
  • io_memoryReset, which resets the memory controller, external memory module, I2C master and slave connected to the memory controller, and any user logic.
  • io_ddrMasters_0_reset, which responds to the reset for AXI slave channel 0 and is synchronized to io_ddrMasters_0_clk.
  • io_ddrMasters_1_reset, which responds to the reset for AXI slave channel 1 and is synchronized to io_ddrMasters_1_clk.

The SoC asserts the io_memoryReset, io_ddrMaster_0_reset, and io_ddrMaster_1_reset signals at the same time to allow the AXI slaves access to the AXI cross bar once the reset completes.

Once io_systemReset goes low, the user binary code is executed.

Table 1. Reset Ports
Port Direction Description
io_asyncReset Input Active-high asynchronous reset for the entire system.
io_systemReset Output Synchronous active-high reset for the system clock (io_systemClk).
io_peripheralReset Output Synchronous active-high reset for the peripheral clock (io_peripheralClock).
io_memoryReset Output External memory reset source from the RISC-V SoC.
io_ddrMasters_0_reset
io_ddrMasters_1_reset
 Output Responds to the reset for the AXI slave.