Functional Description

The Sapphire SoC incorporates 1 to 4 32-bit RISC-V processors that have an instruction cache with up to 8 ways and a configurable size of 1 - 32 KB, a data cache with up to 8 ways and a configurable size of 1 - 32 KB, 1 - 512 KB of on-chip RAM, and a variety of peripherals (including 1 - 5 APB3 slave peripherals and 1 AXI slave). You can configure the operating frequency from 20 - 400 MHz (the actual performance is limited by the design's fMAX). The SoC includes 1 - 3 I2C peripherals, 1 - 3 UARTs, 1 - 3 user timers, 1 - 8 user interrupts, and 1 - 3 SPI masters. The SoC also features a floating-point unit (FPU) and Linux memory management unit (MMU).

The default configuration has up to a 512-bit half-duplex and full-duplex AXI bus to communicate with the Efinix LPDDR4x controller or HyperRAM controller.
  • DDR controller—This core uses the Trion FPGAs hard DDR DRAM interface to reset an external DRAM module (resets and re-initializes the Trion FPGA's DDR interface as well as the DDR module(s)).
  • HyperRAM controller—This core controls HyperRAM memory modules.

You can customize the SoC using the IP Manager in the Efinity® software.

Figure 1. Sapphire SoC Block Diagram

Note: In the Sapphire SoC platform, the DDR memory is managed by a hard memory controller integrated within the device, while HyperRAM is accessed through a soft-core memory controller using an AXI3 half-duplex interface.
  • On Titanium devices, the DDR controller is connected through an AXI4 full-duplex interface, supporting LPDDR4 and LPDDR4X.
  • On Trion devices, the connection uses an AXI3 half-duplex interface, supporting DDR3, LPDDR2, and LPDDR3.
Figure 2. Sapphire SoC with Multiple Cores Block Diagram