Supervisor Status Register (sstatus): 0x100

the sstatus register is a subset of the mstatus register.

31 30 20 19 18 17 16 15 14 13 12 9 8 7 6 5 4 2 1 0
SD Reserved MXR SUM MPRV Reserved FS Reserved SPP Reserved SPIE Reserved SIE Reserved
Bits Field Description Single/Multi-Core w/FPU w/MMU
0 Reserved Reserved. N/A N/A N/A
1 SIE Supervisor global interrupt enable register. N/A N/A Read/Write
2-4 Reserved Reserved. N/A N/A N/A
5 SPIE Supervisor previous interrupt enable register. N/A N/A Read/Write
6-7 Reserved Reserved. N/A N/A N/A
8 SPP Supervisor previous privilege mode. N/A N/A Read/Write
9-12 Reserved Reserved. N/A N/A N/A
13-14 FS Status of the floating-point unit.
2'b00: Off
2'b01: Initial
2'b10: Clean
2'b11: Dirty
 N/A Read/Write N/A
15-16 Reserved Reserved N/A N/A N/A
17 MPRV Modifies the privilege level at which loads and stores the executables.
1'b1: Load and store memory address are translated and protected
1'b0: Normal mode
 N/A N/A Read/Write
18 SUM Modifies the privilege with which S-mode loads and stores access virtual memory.
1'b1: Access permitted
1'b0: S-mode memory accesses to pages that are accessible by U-mode will fault
 N/A N/A Read/Write
19 MXR Modifies the privilege that loads access virtual memory.
1'b1: loads from pages marked with either readable or executable will succeed
1'b0: only loads from page marked readable will succeed
 N/A N/A Read/Write
20-30 Reserved Reserved. N/A N/A N/A
31 SD Indicates the presence of FS field with dirty state that requires saving extended user context to memory. N/A Read/Write N/A