Revision History
| Date | Version | Description |
|---|---|---|
| November 2025 | 6.0 | Updated Titanium, Trion, and
Topaz in Resource Utilization and Performance
and Performance Benchmark in Features. (DOC-2683) Change AXI
master/slave interface 0/1. In Watchdog Timer Interface,
Added Disable Register: 0x0000_0008. Updated Heatbeat Register:
0x0000_0000 and Enable Register: 0x0000_0004. |
| May 2025 | 5.3 | Updated Sapphire SoC Block Diagram and added note in Functional Description. (DOC-2533) |
| May 2025 | 5.2 | Updated Titanium and Trion and adding Topaz in Resource Utilization and Performance and Performance Benchmark in Features. (DOC-2461) |
| January 2025 | 5.1 | Updated number of pins to 32 from 16 for GPIO, Input Register: 0x0000_0000, Output Register: 0x0000_0004, and Output Enable Register: 0x0000_0008. (DOC-2295) |
| December 2024 | 5.0 | Updated Titanium and Trion and
adding Topaz in Resource Utilization and Performance
and Performance Benchmark in Features. (DOC-2098) Added Watchdog
Timer Register Map. Removed vector mode from both Machine
Trap-Vector Base-Address Register (mtvec): 0x305 and Supervisor
Trap-Vector Base Address Register (stvec): 0x305. |
| June 2024 | 4.1 | Updated Titanium and Resource Utilization and Performance and Performance Benchmark in Features. (DOC-1790) |
| December 2023 | 4.0 | Updated Titanium and Resource Utilization and Performance and Performance Benchmark in Features. (DOC-1533) |
| July 2023 | 3.3 | Updated Little-Endian in the topic VexRiscv RISC-V Core. (DOC-1380) |
| June 2023 | 3.2 | Updated the following sections: (DOC-1253) Trion Resource Utilization and Performance
Performance Benchmark 1 and 2 tables. Interrupt
Register: 0x0000_0020 Interrupt Clears Register:
0x0000_0024 Master Status Register:
0x0000_0040 Timeout Register: 0x0000_002C Added
new topics: Slave Status Register:
0x0000_0044 Slave Override Register:
0x0000_0048 |
| January 2023 | 3.1 | Updated of interface details in Features topic and Sapphire RISC-V SoC Design Flow figure. Added
new section in Features topic: Performance
Benchmark. Updated the tables in UART Peripheral Interface
→ Status Register: 0x0000_0004, Config Register: 0x0000_000C, Error
Break Register: 0x0000_0010. Updated tables in User Timer
→ Prescaler Register: 0x0000_0000 and Timer Configuration Register:
0x0000_0040. Changed main topic title of Machine-Level ISA
to Machine-Level CSR. Updated all topics in Machine-Level
CSR. Added new main topic Supervisor-Level
CSR. |
| August 2022 | 3.0 | Updated to add multi-core support specifications. Added clint
description and registers. Added mscratch
register. |
| June 2022 | 2.2 | The VexRiscv core used in the Sapphire SoC has six pipeline stages. |
| February 2022 | 2.1 | Updated the Config Register for the SPI Master Peripheral Interface. (DOC-692) |
| December 2021 | 2.0 | The SoC now supports a floating point unit, Linux memory management
unit, custom instruction, and optional RISC-V extensions such as atomic
and compressed. The SoC has a core timer and up to 3 user timers.
The machine timer is removed. The SoC has an optional I/O
peripheral clock and reset for clocking the APB3 peripherals.
The address map parameters have
changed. Clarified AXI interface description.
(DOC-633) |
| September 2021 | 1.1 | The SoC minimum frequency changed to 20 MHz. (DOC-544) Updated
resource utilization and performance. (DOC-544) The APB
slave size is configurable. (DOC-544) The AXI slave size
is 256 MB maximum. (DOC-544) |
| July 2021 | 1.0 | Initial release. |