Features

  • 1 - 4 (user selectable) VexRiscv processor(s) with 6 pipeline stages (fetch, injector, decode, execute, memory, and write back), interrupts and exception handling with machine mode
  • 20 - 400 MHz system clock frequency
  • 1 - 512 KB on-chip RAM with boot loader for SPI flash
  • Memory controller for DDR3, LPDDR4x or HyperRAM memories
    • Supports memory module sizes from 4 MB to 3.5 GB
    • User-configurable external memory bus frequency
    • 1 half-duplex AXI3 interface (up to 512-bits) or 1 full-duplex AXI4 interface (up to 512-bits) to communicate with the external memory
    • 400 MHz DDR3 clock frequency, 800 Mbps
    • 1089 MHz LPDDR4x clock frequency, 2178 Mbps
    • 250 MHz HyperRAM clock frequency, 500 Mbps
  • Up to 2 AXI slave channels for user logic, data widths from 32 to 512
  • 1 AXI master channel to user logic
  • Includes an optional multi-way instruction and Data Cache
  • Includes a floating point unit (FPU)
  • Includes an optional Linux memory management unit (MMU)
  • Includes an optional custom instruction interface with 1,024 IDs to perform various functions
  • Supports optional RISC-V extensions such as atomic and compressed
  • APB3 peripherals:
    • Up to 32 GPIOs
    • Up to 3 I2C masters
    • Clint timer
    • Platform-level interrupt controller (PLIC)
    • Up to 3 SPI masters
    • Up to 3 user timers
    • Up to 3 UARTs with 115,200 baud rate
    • Up to 5 slave user peripherals
    • Up to 8 user interrupts

FPGA Support

The Sapphire SoC supports all Trion® FPGAs (except the T4) and all Titanium FPGAs, however, you may only be able to use some of the features in certain devices. For example, the DDR controller only works with FPGAs that have a hardened DDR controller block.

Titanium Resource Utilization and Performance

The Sapphire is configurable. These tables show the resource usage for various configurations.

Table 1. Cacheless SoC with External MemoryStandard option
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 7,166 7,672 44 4 382 2025.2
Ti60 F225 C4 (custom instruction) 7,138 7,719 44 4 376 2025.2
Table 2. Cacheless SoC without External MemoryStandard option
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 4,467 3,117 12 4 387 2025.2
Ti60 F225 C4 (custom instruction) 4,585 3,159 12 4 393 2025.2
Table 3. Cached SoC with External MemoryStandard option
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 7,560 8,110 56 4 401 2025.2
Ti60 F225 C4 (custom instruction) 7,603 8,150 56 4 406 2025.2
Ti60 F225 C4 (FPU) 14,008 12,240 77 13 278 2025.2
Ti60 F225 C4 (2 cores) 14,009 13,181 103 8 325 2025.2
Ti60 F225 C4 (3 cores) 18,821 15,521 127 12 344 2025.2
Ti60 F225 C4 (4 cores) 22,078 17,795 150 16 301 2025.2

Table 4. Cached SoC without External MemoryStandard option
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (typical) 4,911 3,539 24 4 400 2025.2
Ti60 F225 C4 (custom instruction) 4,978 3,582 24 4 407 2025.2
Ti60 F225 C4 (FPU) 11,531 7,681 44 13 290 2025.2
Ti60 F225 C4 (2 cores) 11,376 8,302 62 8 363 2025.2
Ti60 F225 C4 (3 cores) 15,597 10,630 87 12 334 2025.2
Ti60 F225 C4 (4 cores) 20,020 12,888 110 16 335 2025.2
Table 5. Cacheless SoCLite option
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (external memory) 3,311 2,789 14 0 383 2025.2
Ti60 F225 C4 (internal memory) 2,761 1,957 24 0 412 2025.2
Table 6. Cached SoCLite option
FPGA Logic/Adders FlipFlops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Ti60 F225 C4 (external memory) 3,750 2,978 26 0 394 2025.2
Ti60 F225 C4 (internal memory) 3,164 2,131 36 0 418 2025.2

Trion Resource Utilization and Performance

The Sapphire is configurable. These tables show the resource usage for various configurations.

Table 7. Cacheless SoC with External MemoryStandard option
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 7,045 7,815 48 4 105 2025.2
T120 F324 (custom instruction) 7,135 7,861 48 4 109 2025.2
Table 8. Cacheless SoC without External MemoryStandard option
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 4,498 3,256 16 4 116 2025.2
T120 F324 (custom instruction) 4,556 3,298 16 4 109 2025.2
Table 9. Cached SoC with External MemoryStandard option
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 7,391 8,257 67 4 115 2025.2
T120 F324 (custom instruction) 7,619 8,305 67 4 115 2025.2
T120 F324 (FPU) 14,406 12,499 80 29 79 2025.2
T120 F324 (2 cores) 14,048 13,456 109 8 98 2025.2
T120 F324 (3 cores) 18,245 15,929 136 12 93 2025.2
T120 F324 (4 cores) 22,989 18,334 162 16 88 2025.2
Table 10. Cached SoC without External MemoryStandard option
FPGA Logic /Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (typical) 5,006 3,677 35 4 116 2025.2
T120 F324 (custom instruction) 5,101 3,722 35 4 117 2025.2
T120 F324 (FPU) 11,620 7,938 47 29 88 2025.2
T120 F324 (2 cores) 11,342 8,570 68 8 95 2025.2
T120 F324 (3 cores) 15,561 11,035 96 12 90 2025.2
T120 F324 (4 cores) 19,988 13,425 122 16 92 2025.2
Table 11. Cacheless SoCLite option
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (external memory) 3,344 2,805 18 0 113 2025.2
T120 F324 (internal memory) 2,753 1,964 40 0 110 2025.2
Table 12. Cached SoCLite option
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
T120 F324 (external memory) 3,624 3,023 37 0 106 2025.2
T120 F324 (internal memory) 3,187 2,171 59 0 125 2025.2

Topaz Resource Utilization and Performance

The Sapphire is configurable. These tables show the resource usage for various configurations.

Table 13. Cacheless SoC with External MemoryStandard option
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (typical) 7,166 7,672 44 4 265 2025.2
Tz110 J484 C3 (custom instruction) 7,138 7,719 44 4 265 2025.2
Table 14. Cacheless SoC without External MemoryStandard option
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (typical) 4,467 3,117 12 4 244 2025.2
Tz110 J484 C3 (custom instruction) 4,585 3,159 12 4 262 2025.2
Table 15. Cached SoC with External MemoryStandard option
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (typical) 7,560 8,110 56 4 258 2025.2
Tz110 J484 C3 (custom instruction) 7,603 8,150 56 4 260 2025.2
Tz110 J484 C3 (FPU) 14,008 12,240 77 13 199 2025.2
Tz110 J484 C3 (2 cores) 14,009 13,181 103 8 211 2025.2
Tz110 J484 C3 (3 cores) 18,821 15,521 127 12 207 2025.2
Tz110 J484 C3 (4 cores) 22,078 17,795 150 16 193 2025.2
Table 16. Cached SoC without External MemoryStandard option
FPGA Logic /Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110J484 C3 (typical) 4,991 3,539 24 4 254 2025.2
Tz110 J484 C3 (custom instruction) 4,978 3,582 24 4 253 2025.2
Tz110 J484 C3 (FPU) 11,531 7,681 44 13 200 2025.2
Tz110 J484 C3 (2 cores) 11,376 8,302 62 8 232 2025.2
Tz110 J484 C3 (3 cores) 15,597 10,630 87 12 222 2025.2
Tz110 J484 C3 (4 cores) 20,020 12,888 110 16 224 2025.2
Table 17. Cacheless SoCLite option
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (external memory) 3,311 2,789 14 0 251 2025.2
Tz110 J484 C3 (internal memory) 2,761 1,957 24 0 266 2025.2
Table 18. Cached SoCLite option
FPGA Logic/Adders FlipFlops Memory Blocks DSP Blocks fMAX (MHz) Efinity Version
Tz110 J484 C3 (external memory) 3,750 2.978 26 0 267 2025.2
Tz110 J484 C3 (internal memory) 3,164 2,131 36 0 274 2025.2

Performance Benchmark

The performance of the CPU can be benchmarked with Dhrystone and Coremark benchmark programs for easier comparison between processors. While the Sapphire SoC uses the same VexRiscv core, the configurations such as memory, cache, and additional extensions would affect the performance of the system. The Dhrystone and CoreMark scores for each of the configurations are tabulated in the table based on Trion T120 F324 Development Board.

Development board: Trion T120 F324

Efinity version 2024.1

Table 19. Performance Benchmark 1Constants: Frequency @ 50 MHz with External Memory (DDR3), Legend: 1 = Enabled; 0 = Disabled
Option Cache Instruction and Data Way (kB) Instruction and Data Size (kB) FPU Atomic Compressed Coremark (/MHz) Dhrystone (/MHz)
Standard 1 1 4 0 0 0 1.82 0.89
Standard 1 4 4 0 0 0 1.85 1.05
Standard 1 8 32 0 0 0 1.90 1.05
Standard 1 1 4 1 0 0 1.82 0.90
Standard 1 4 4 0 1 1 1.81 1.03
Standard 1 4 4 1 0 0 1.86 1.05
Standard 0 1 4 0 0 0 0.23 0.12
Lite 1 1 4 0 0 0 0.62 0.59
Lite 0 1 4 0 0 0 0.13 0.14
Table 20. Performance Benchmark 2Constants: Frequency @ 50 MHz with Internal Memory, Legend: 1 = Enabled; 0 = Disabled
Option Cache Instruction and Data Way (kB) Instruction and Data Size (kB) FPU Atomic Compressed Coremark (/MHz) Dhrystone (/MHz)
Standard 1 1 4 0 0 0 1.86 0.97
Standard 1 4 4 0 0 0 1.88 1.05
Standard 1 8 32 0 0 0 1.90 1.05
Standard 1 1 4 1 0 0 1.86 0.99
Standard 1 4 4 0 1 1 1.85 1.03
Standard 1 4 4 1 0 0 1.88 1.06
Standard 0 1 4 0 0 0 1.69 0.86
Lite 1 1 4 0 0 0 0.62 0.71
Lite 0 1 4 0 0 0 0.60 0.75