SPI Master Peripheral Interface

The SPI master peripheral interface supports traditional dual-line full-duplex mode as well as half-duplex mode in 2 and 4-wire SPI. The SPI data width is configurable up to 16 bits. Half-duplex mode is only available when the SPI data width is configured as 8 or 16. When implementing the SPI peripheral in traditional dual-line mode, use the data_0 ports as MOSI and and the data_1 ports as MISO.

Table 1. SPI Master PortsWhere n is 0, 1, or 2

Port	Direction	Description
system_spi_n_io_sclk_write	Output	SPI SCK.
system_spi_n_io_data_0_writeEnable	Output	SPI output enable for data 0.
system_spi_n_io_data_0_read	Input	SPI input for data 0.
system_spi_n_io_data_0_write	Output	SPI output for data 0.
system_spi_n_io_data_1_writeEnable	Output	SPI output enable for data 1.
system_spi_n_io_data_1_read	Input	SPI input for data 1.
system_spi_n_io_data_1_write	Output	SPI output for data 1.
system_spi_n_io_data_2_writeEnable	Output	SPI output enable for data 2.
system_spi_n_io_data_2_read	Input	SPI input for data 2.
system_spi_n_io_data_2_write	Output	SPI output for data 2.
system_spi_n_io_data_3_read	Input	SPI input for data 3.
system_spi_n_io_data_3_write	Output	SPI output for data 3.
system_spi_n_io_data_3_writeEnable	Output	SPI output enable for data 3.
system_spi_n_io_ss	Output	SPI SS.

Table 2. SPI Master Register Map

Address Offset	Register Name	Privilege	Width
0x0000_0000	Cmd	Read/Write	32
0x0000_0004	RSP	Read	32
0x0000_0008	Config	Write	32
0x0000_000C	Interrupt	Read/Write	32
0x0000_0020	ClockDivider	Write	32
0x0000_0024	ssSetup	Write	32
0x0000_0028	ssHold	Write	32
0x0000_002C	ssDisable	Write	32
0x0000_0030	ssActiveHigh	Write	32
0x0000_0050	cmd_writeLarge	Write	32
0x0000_0054	cmd_readWriteLarge	Write	32
0x0000_0058	cmd_readLarge	Read	32