ssSetup Register: 0x0000_0024
| 31 | 12 | 11 | 0 | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Reserved | ssSetup | ||||||||||||||
| Bits | Field | Description | Privilege |
|---|---|---|---|
| 0-11 | ssSetup | Clock cycle between activated chip-select and first rising-edge of
SCLK. Clock cycle refers to FCLK. |
Write |
| 12-31 | Reserved | Reserved. | N/A |
