Interrupt Clears Register: 0x0000_0024
| 31 | 18 | 17 | 16 | 15 | 14 | 8 | 7 | 6 | 5 | 4 | 3 | 0 | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Reserved | filterFlag | clockGenEnterFlag | clockGenExitFlag | Reserved | dropFlag | endFlag | restartFlag | startFlag | Reserved | ||||||||||||||||
| Bits | Field | Description | Privilege |
|---|---|---|---|
| 0-3 | Reserved | Reserved. | N/A |
| 4 | startFlag | Start interrupt status. 1'b1: A transfer is in START
state Write 1'b1 to clear the flag. |
Read/Write |
| 5 | restartFlag | Restart interrupt status. 1'b1: A transfer is
restarted Write 1'b1 to clear the flag. |
Read/Write |
| 6 | endFlag | End interrupt status. 1'b1: A transfer is in STOP
state Write 1'b1 to clear the flag. |
Read/Write |
| 7 | dropFlag | Drop interrupt status. 1'b1: A transfer is
dropped Write 1'b1 to clear the flag. |
Read/Write |
| 8 - 14 | Reserved | Reserved. | N/A |
| 15 | clockGenExitFlag | Master clock generation exit interrupt status. 1'b1: Controller
stops generating output clock. Write 1'b1 to clear the
flag. |
Read/Write |
| 16 | clockGenEnterFlag | Master clock generation enterinterrupt status. 1'b1: Controller
starts generating output clock. Write 1'b1 to clear the
flag. |
Read/Write |
| 17 | filterFlag | Address filter interrupt status. 1'b1: Controller as slave and
its address filter is triggered Write 1'b1 to clear the
flag.
|
Read/Write |
| 18-31 | Reserved | Reserved. | N/A |