Interrupt Register: 0x0000_0020

31									18	17	16	15	14						8	7	6	5	4	3	2	1	0
Reserved										filterEnable	clockGenEnterEnable	clockGenExitEnable	Reserved							dropEnable	endEnable	restartEnable	startEnable	txAckEnable	txDataEnable	rxAckEnable	rxDataEnable

Bits	Field	Description	Privilege
0	rxDataEnable	Write 1'b1 to enable interrupt when valid data is received.	Read/Write
1	rxAckEnable	Write 1'b1 to enable interrupt when valid acknowledge bit is received.	Read/Write
2	txDataEnable	Write 1'b1 to enable interrupt when valid data is transmitted.	Read/Write
3	txAckEnable	Write 1'b1 to enable interrupt when valid acknowledge bit is transmitted.	Read/Write
4	startEnable	Write 1'b1 to enable interrupt when a transfer is in START state.	Read/Write
5	restartEnable	Write 1'b1 to enable interrupt when a transfer is restarted.	Read/Write
6	endEnable	Write 1'b1 to enable interrupt when a transfer is in STOP state.	Read/Write
7	dropEnable	Write 1'b1 to enable interrupt when a transfer is dropped due to confilct or timeout.	Read/Write
8-14	Reserved	Reserved.	N/A
15	clockGenExitEnable	Write 1'b1 to enable interrupt when the controller stops generating clock output.	Read/Write
16	clockGenEnterEnable	Write 1'b1 to enable interrupt when the controller starts generating clock input.	Read/Write
17	filterEnable	Write 1'b1 to enable interrupt when the controller acts as slave and its address filter is triggered.	Read/Write
18-31	Reserved	Reserved.	N/A