ssDisable Register: 0x0000_002C

31							12	11							0
Reserved								ssDisable

Bits	Field	Description	Privilege
0-11	ssDisable	Clock cycle delay refers to the system clock (io_systemClk) before the next chip select can be activated. If you enable the peripheral clock, the clock cycle will refer to the peripheral clock (io_peripheralClk).	Write
12-31	Reserved	Reserved.	N/A