Sampling Clock Divider Register: 0x0000_0028
| 31 | 10 | 9 | 0 | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Reserved | samplingClockDivider | |||||||||||||||||||||||||||
| Bits | Field | Description | Privilege |
|---|---|---|---|
| 0-9 | samplingClockDivider | Sampling rate = (FCLK/(samplingClockDivider + 1) Controls the
rate at which the I2C controller samples SCL and SDA. FCLK
is the system clock (io_systemClk) to the SoC. If you enable the
peripheral clock, then FCLK is driven by the peripheral clock
(io_peripheralClk) instead. |
Write |
| 10-31 | Reserved | Reserved. | N/A |