The mcause register is a 32-bit read-write register. When a trap is
taken into M-mode, mcause is written with a code indicating the event
that caused the trap. Otherwise, mcause is never written by the
implementation, though it may be explicitly written by software.
| 31 |
30 |
|
|
|
|
|
|
|
|
|
0 |
| Interrupt |
Exception Code |
| Bits |
Field |
Description |
Single/Multi-Core |
w/FPU |
w/MMU |
| 0-30 |
Exception code |
See Table 1. |
Read |
Read |
Read |
| 31 |
Interrupt |
mcause interrupt bit. |
Read |
Read |
Read |
Table 1. Machine Cause Register (mcause) Values after Trap
| Interrupt |
Exception Code |
Description |
| 1 |
0 |
Reserved. |
| 1 |
1 |
Supervisor software interrupt. |
| 1 |
2 |
Reserved. |
| 1 |
3 |
Machine software interrupt. |
| 1 |
4 |
User timer interrupt. |
| 1 |
5 |
Supervisor timer interrupt. |
| 1 |
6 |
Reserved. |
| 1 |
7 |
Machine timer interrupt. |
| 1 |
8 |
User external interrupt. |
| 1 |
9 |
Supervisor external interrupt. |
| 1 |
10 |
Reserved. |
| 1 |
11 |
Machine external interrupt. |
| 1 |
≥12 |
Reserved. |
| 0 |
0 |
Instruction address misaligned. |
| 0 |
1 |
Instruction access fault. |
| 0 |
2 |
Illegal instruction. |
| 0 |
3 |
Breakpoint. |
| 0 |
4 |
Load address misaligned. |
| 0 |
5 |
Load access fault. |
| 0 |
6 |
Store/AMO address misaligned. |
| 0 |
7 |
Store/AMO access fault. |
| 0 |
8 |
Reserved. |
| 0 |
9 |
Reserved. |
| 0 |
10 |
Reserved. |
| 0 |
11 |
Environment call from M-mode. |
| 0 |
12 |
Instruction page fault. |
| 0 |
13 |
Load page fault. |
| 0 |
14 |
Reserved. |
| 0 |
15 |
Store/AMO page fault. |
| 0 |
≥16 |
Reserved. |