Introduction

Efinix provides a hardened RISC-V SoC, called Sapphire High-Performance SoC, that you can implement in tandem with the soft logic block on the Titanium Ti375 FPGA.

This hardened SoC features a 32-bit quad-core RISC-V processor based on the RISCV32I ISA1 with M, A, C, F, and D extensions. It operates with six pipeline stages: fetch, injector, decode, execute, memory, and writeback.

Each CPU core includes a dedicated FPU and supports custom instructions. The processor follows the standard RISC-V debug specification and providing 8 hardware breakpoints. Additionally, it supports machine and supervisor privileged modes, along with Linux MMU SV32 page-based virtual memory.

This user guide describes how to:
  • Build RTL designs using the Sapphire High-Performance RISC-V SoC using an example design targeting Titanium Ti375 C529 Development Board, and how to extend the example for your own application.
  • Set up the software development environment using an example project, create your own software based on example projects, and use the API.
Figure 1. Designing Hardware and Software for the Sapphire High-Performance RISC-V SoC
Notice: Refer to the Sapphire High-Performance RISC-V SoC Data Sheet for detailed specifications on the SoC.
1 ISA: Instruction Set Architecture