Revision History

Corrected statement in PLL Auto Calibration Flow and flow information in Calibration Flow Diagram.

Corrected Calibration Scheme, Write Buffer Depth, and Read Buffer Depth in table HyperRAM Controller Core Parameters (Memory Tab).

Updated Interface Designer Settings for PLL Auto Calibration and PLL Manual Calibration.

Added Memory Operating Frequency of 250 MHz and added a note in Customizing the HyperRAM Controller.

Added dynamic reconfiguration and hybrid sleep in Features. (DOC-2745)

Added new topic On-Demand Calibration, Dynamic Reconfiguration for Configuration Register, and Configuration Register.

In Customizing the HyperRAM Controller, added Calibration Scheme and removed Calibration Mode, Periodic Calibration, and Periodic Calibration Signal in table HyperRAM Controller Core Parameters (Memory Tab). Added Configuration Register Control in table HyperRAM Controller Core Parameters (Memory Register Tab)

Added table Periodic Calibration User Ports in Ports.

Updated values for io_arw_payload_burst [1:0] in HyperRAM Controller AXI Ports. Added additional descriptions for native_ram_address. (DOC-2648)

Updated boundary values in table 512 Mb HyperRAM Native Address Boundary.

Added IP Version in Revision History. (DOC-2185)

Updated Table 1, Table 2, Introduction, Features, topic AXI Adressing, and Native User Interface. (DOC-2097)

Added topic Periodic Recalibration Flow, Table 2, and Table 1.

Removed soft logic calibration block diagram and Soft Logic Calibration topic.

Removed Trion. Added Topaz in Device Support and document.

Added feature Dual HyperRAM support.

Added figure HyperRAM Controller Dual HyperRAM Block Diagram.

Updated table HyperRAM Controller Ports with second HyperRAM ports, AXI Address Conversion Ratio, and HyperRAM Controller Core Parameters (Memory Tab) for Dual HyperRAM.

Updated figure HyperRAM Controller PLL Calibration Block Diagram and HyperRAM Controller PLL Manual Calibration Block Diagram with hbc_cal_debug_info[26:0].

Updated Resource Utilization and Performance.

Updated figures HyperRAM Controller PLL Calibration Block Diagram, HyperRAM Controller PLL Manual Calibration Block Diagram, and HyperRAM Controller Soft Logic Calibration Block Diagram (change to hbc_cal_debug_info[23:0]).

Added Bit [23:16] are reserved in table HyperRAM Controller Ports (hbc_cal_debug_info[15:0]), HyperRAM Controller Core Parameters (Memory Tab), and Virtual I/O Sources and Probes.

Updated topic PLL Auto Calibration Flow and figure Calibration Flow Diagram, topic PLL Manual Calibration Flow.

Changed sub-topic AXI Interface to Hyperbus Interface, figure name of AXI Interface Write Operation Waveform and AXI Interface Read Operation Waveform to Hyperbus Write Operation Waveform and Hyperbus Read Operation Waveform. (DOC-1825)

Added new paragraph in Native User Interface topic.

Updated figure Native Interface Write Operation Waveform.

Updated supported data rate. (DOC-1535)

Corrected hbc_rwds_OUT_HI and hbc_rwds_OUT_LO signal widths. (DOC-1236)

Corrected native_wr_data and native_rd_data ports widths.

Added note about only one HyperRAM Controller can be instantiated for a single device. (DOC-909)

Updated native port descriptions, added FIFO depth size calculation, and added native mode operation waveform. (DOC-846)

Updated resource utilization table. (DOC-700)

Added support for native user interface.

Updated parameters supported in IP Manager.

Updated HyperRAM Controller ports.

Updated example design.

Updated design example target board to production Titanium Ti60 F225 Development Board and updated Resource Utilization and Performance, and Example Design Implementation tables. (DOC-553)