Configuration Register 0

Table 1. Configuration Register 0 Bit Assignments
CR0 Bit Function Settings (Binary)
[15] Deep Power Down Enable 1b: Normal operation (default)
0b: Writing 0 to CR0[15] causes the device to enter deep power down (DPD)
HyperRAM automatically sets the value of CR0[15] to 1 after exiting the DPD.
Warning: Contents of configuration register are lost when using deep power down, rewriting the registers with the proper setting is needed upon exiting deep power down.
[14:12] Drive Strength 000b: 34 ohms (default)
001b: 115 ohms
010b: 67 ohms
011b: 46 ohms
100b: 34 ohms
101b: 27 ohms
110b: 22 ohms
111b: 19 ohms
[11:8] Reserved 1b: Reserved (default)
When writing this register, this bit should be kept 1b.
[7:4] Initial Latency 0000b: 5 Clock Latency at 133MHz maximum frequency
0001b: 6 Clock Latency at 166MHz maximum frequency
0010b: 7 Clock Latency at 200MHz maximum frequency (default)
0010b: 7 Clock Latency at 250MHz maximum frequency
0011b: Reserved
0100b: Reserved
...
1101b: Reserved
1110b: 3 Clock Latency at 85MHz maximum frequency
1111b: 4 Clock Latency at 104MHz maximum frequency
Warning: Do not change the initial latency when performing dynamic configuration register reconfiguration.
[3] Fixed Latency Enable 0b: Variable Latency—1 or 2 times Initial latency depending on RWDS during CA cycles.
1b: Fixed 2 times Initial Latency (default). For multi-die stacking only fixed latency is allowed.
Variable Latency is not supported by the HyperRAM Controller core IP. This bit must be set to 1 when performing configuration register write.
[2] Hybrid Burst Enable 0b: Wrapped burst sequences to follow hybrid burst sequencing
1b: Wrapped burst sequences in legacy wrapped burst manner (default)
[1:0] Burst Length 00b: 128
01b: 64
10b: 16
11b: 32 (default)