Ports

Table 1. HyperRAM Controller Ports
Port Direction Description
hbc_cs_n Output Bus transactions are initiated with a logic high-to-low transition. Bus transactions are terminated with a logic low-to-high transition. The master device has a separate CS# signal for each slave.
rst Input Core asynchronous reset, active high.
ram_clk Input RAM operating clock.
ram_clk_cal Input RAM calibration clock.
Used for PLL auto and manual calibration only.
ram_clk_cal_2 Input RAM 2 calibration clock.
Used for Dual HyperRAM with PLL auto calibration only.
hbc_rst_n Output When logic low, the slave device self-initializes and returns to the standby state.
RWDS and DQ signals are placed into the high-Z state when the RESET# signal is low.
hbc_cal_pass Output Indicates calibration is passing.
hbc_cs_n_2 Output Chip select for second HyperRAM.
hbc_rst_n_2 Output When logic low, the slave device self-initializes and returns to the standby state. RWDS and DQ signals are placed into the high-Z state when the RESET# signal is low.
hbc_ck_p_HI_2 Output Differential Clock:
Command, address, and data information is output with respect to the crossing of the CK and CK# signals for second HyperRAM.
Single Ended Clock:
CK# is not used, only a single ended CK is used. The clock is not required to be free-running.
hbc_ck_p_LO_2 Output
hbc_ck_n_HI_2 Output
hbc_ck_n_LO_2 Output
hbc_dq_OUT_HI_2 [n-1:0] Output DQ output ports for command, address, and data for second HyperRAM.
n = 8 (x8 mode), 16 (x16 mode)
hbc_dq_OUT_LO_2 [n-1:0] Output
hbc_dq_OE_2 [n-1:0] Output DQ output enable port for second HyperRAM.
n = 8 (x8 mode), 16 (x16 mode)
hbc_dq_IN_HI_2 [n-1:0] Input DQ input ports for data for second HyperRAM.
n = 8 (x8 mode), 16 (x16 mode)
hbc_dq_IN_LO_2 [n-1:0] Input
hbc_rwds_OUT_HI_2 [m-1:0] Output RWDS output ports for data mask during write operation for second HyperRAM.
m = 1 (x8 mode), 2 (x16 mode)
hbc_rwds_OUT_LO_2 [m-1:0] Output
hbc_rwds_OE_2 [m-1:0] Output RWDS output enable port for second HyperRAM.
m = 1 (x8 mode), 2 (x16 mode)
hbc_rwds_IN_HI_2 [m-1:0] Input RWDS input enable port for second HyperRAM.
m = 1 (x8 mode), 2 (x16 mode)
hbc_rwds_IN_LO_2 [m-1:0] Input
hbc_cal_debug_info [26:0] Output
Bit Description
26:19 Delay steps that received matched calibration data by second HyperRAM.
One-hot encoded
Bit 0: Delay step 0 received matched data
Bit 1: Delay step 1 received matched data
Bit 2: Delay step 2 received matched data
Bit 3: Delay step 3 received matched data
Bit 4: Delay step 4 received matched data
Bit 5: Delay step 5 received matched data
Bit 6: Delay step 6 received matched data
Bit 7: Delay step 7 received matched data
18:16 Locked down PLL phase shifted step for second HyperRAM.
15:8
Delay steps that received matched calibration data.
One-hot encoded.
Bit 0: Delay step 0 received matched data
Bit 1: Delay step 1 received matched data
Bit 2: Delay step 2 received matched data
Bit 3: Delay step 3 received matched data
Bit 4: Delay step 4 received matched data
Bit 5: Delay step 5 received matched data
Bit 6: Delay step 6 received matched data
Bit 7: Delay step 7 received matched data
7:5 Locked down PLL phase shifted step
1 Calibration pass
0 Calibration done
hbc_ck_p_HI Output Differential Clock:
Command, address, and data information is output with respect to the crossing of the CK and CK# signals.
Single Ended Clock:
CK# is not used, only a single ended CK is used. The clock is not required to be free-running.
hbc_ck_p_LO Output
hbc_ck_n_HI Output
hbc_ck_n_LO Output
hbc_dq_OUT_HI [n-1:0] Output DQ output ports for command, address, and data.
n = 8 (x8 mode), 16 (x16 mode)
hbc_dq_OUT_LO [n-1:0] Output
hbc_dq_OE [n-1:0] Output DQ output enable port.
n = 8 (x8 mode), 16 (x16 mode)
hbc_dq_IN_HI [n-1:0] Input DQ input ports for data.
n = 8 (x8 mode), 16 (x16 mode)
hbc_dq_IN_LO[n-1:0] Input
hbc_rwds_OUT_HI [m-1:0] Output RWDS output ports for data mask during write operation.
m = 1 (x8 mode), 2 (x16 mode)
hbc_rwds_OUT_LO [m-1:0] Output
hbc_rwds_IN_HI [m-1:0] Input RWDS input ports for latency indication, also center-aligned reference strobe for read data.
m = 1 (x8 mode), 2 (x16 mode)
hbc_rwds_IN_LO [m-1:0] Input RWDS input ports for latency indication, also center-aligned reference strobe for read data.
m = 1 (x8 mode), 2 (x16 mode)
Applicable in PLL auto and manual calibration only.
hbc_rwds_OE [m-1:0] Output RWDS output enable port.
m = 1 (x8 mode), 2 (x16 mode)
hbc_cal_SHIFT_ENA Output Enables PLL dynamic shifting.
Applicable in PLL auto and manual calibration only.
hbc_cal_SHIFT_SEL[4:0] Output Selects PLL output.
Applicable in PLL auto and manual calibration only.
hbc_cal_SHIFT[2:0] Output Delay steps value.
Applicable in PLL auto and manual calibration only.
dyn_pll_phase_en Input Enable PLL phase adjustment. Used for PLL manual calibration only.
1'b0: Disable
1'b1: Enable
dyn_pll_phase_sel [2:0] Input PLL phase adjustment. 8 steps of the PLL dynamic phase shift settings. Used for PLL manual calibration only.
Table 2. HyperRAM Controller AXI Ports
Port Direction Description
io_axi_clk Input AXI interface operating frequency.
io_arw_valid Input Indicates that the channel is signaling a valid write/read address and control information.
io_arw_ready Output Indicates that the controller is ready to accept an address and associated control signals.
io_arw_payload_addr [31:0] Input The write address gives the address of the first transfer in a write/read burst transaction.
Note: Bit io_arw_payload_addr [31] is reserved. Set this bit to zero.
io_arw_payload_id [7:0] Input Identification tag for the write/read address group of signals.
Note: HyperRAM AXI does not support address reordering or data interleaving.
io_arw_payload_len [7:0] Input Burst length. Indicates the exact number of transfers in a burst. Determines the number of data transfers associated with the address.
Effective burst length = io_arw_payload_len + 1
io_arw_payload_size [2:0] Input Burst size. Indicates the size of each transfer in the burst.
3'b000: 1
3'b001: 2
3'b010: 4
3'b011: 8
3'b100: 16
3'b101: 32
3'b110: 64
3'b111: 128
io_arw_payload_burst [1:0] Input Burst type. The burst type and the size information, determines how the address for each transfer within the burst is calculated. The controller does not support fixed burst.
2'b01: Linear burst
2'b00, 2'b10: Wrap burst
io_arw_payload_lock Input Reserved.
io_arw_payload_write Input Indicates the channel is accepting a write or read transfer.
1'b0: Read
1'b1: Write
io_w_payload_id [7:0] Input ID tag of the write data transfer. Information is not used by the controller.
Note: HyperRAM Controller core's AXI channel does not support address reordering or data interleaving.
io_w_valid Input Write valid. Indicates that valid write data and strobes are available.
io_w_ready Output Write ready. Indicates that the slave can accept the write data.
io_w_payload_data [n-1:0] Input Write data.
n = AXI_DBW
io_w_payload_strb [n-1:0] Input Write strobes. Indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus.
n = AXI_DBW/8
io_w_payload_last Input Write last. Indicates the last transfer in a write burst.
io_b_valid Input Write response valid. Indicates that the channel is signaling a valid write response.
io_b_ready Output Response ready. Indicates that the master can accept a write response.
io_b_payload_id [7:0] Output Response ID tag. ID tag of the write response.
Note: HyperRAM Controller core's AXI channel does not support address reordering or data interleaving.
io_r_valid Output Read address valid. Indicates that the channel is signaling valid read address and control information.
io_r_ready Input Read ready. Indicates that the master can accept the read data and response information.
io_r_payload_data Output Read data.
io_r_payload_id [7:0] Output Read ID tag. Identification tag for the read data group of signals generated by the controller.
io_r_payload_resp [1:0] Output Read response. Indicates the status of the read transfer. This controller only responds ‘b00 or OKAY.
io_r_payload_last Output Read last. Indicates the last transfer in a read burst.
Table 3. HyperRAM Controller Native Ports
Port Direction Description
native_ram_rdwr Input HyperRAM write/read control.
1'b0 : Target for write
1'b1 : Target for read
native_ram_en Input Initiate a single pulse to trigger controller write/read to HyperRAM.
For write operation, you must ensure that the data stored in the write buffer fulfills the configured burst length requirement before pulsing the signal.
After pulsing the signal, monitor the native_ctrl_idle signal transit into low state to indicate the controller has started to process the request.
native_ram_burst_len [11:0] Input HyperRAM transaction burst length.
You can dynamically change the burst length to maximize the transfer efficiency while still fulfilling the memory CS# maximum low time, 4 μs (typical).
The burst length number must not exceed the CS# maximum low time which is governed by the HyperRAM specification.
FIFO Depth Size = ((DQ Width * 2)/ Data width) * native_ram_burst_len
For example: 512 burst length with x16 RAM at 200 MHz will have approximately 2.6 μs CS# low time.
Note: Refer to Ti60/Ti35 data sheet for the tCSM specification (CS# low) if you are working with the HyperRAM in F100S3F2.
native_ram_address [31:0] Input HyperRAM write/read address. The address width depends on the memory density.
native_ram_address [31] =
1: Linear burst (default)
0: Reserved
native_ram_address [30] =
1: Reserved
0: Memory space (default)
native_wr_en Input Buffer write enable. Assert this signal when you want to place the write data into the write buffer.
You can fill-in the write buffer at any time if the write buffer is not full indicated by the native_wr_buf_ready signal.
native_wr_data [n-1:0] Input Write data is placed in the write buffer before the native_ram_en signal is pulsed.
n = AXI_DBW
native_wr_datamask [n/8-1:0] Input Write data mask. Set all to logic low if you do not use the write data mask. Otherwise, drive the signal per data byte (8 bits) granularity.
n = AXI_DBW
native_rd_data[n-1:0] Output Read data width.
n = AXI_DBW
native_rd_valid Output Read valid indicator. Logic high indicates that the returning data is valid.
native_ctrl_idle Output Logic high indicates that the controller is in idle mode.
After you issue the native_ram_en signal, this signal will take multiple cycles to respond due to the clock domain crossing operation. Ensure that the signal is deasserted after issuing a write or read operation.
native_wr_buf_ready Output Write buffer availability. Logic low indicates that the write buffer is full and the write buffer ignores any incoming write data.
Table 4. Periodic Calibration User Ports
Port Direction Description
prd_cal_req Output Periodic calibration request signal. Serves as status pin when On-Demand Calibration is selected.
Domain: io_axi_clk / native_clk
prd_cal_ack Input Periodic calibration acknowledge signal. Used to trigger calibration when On-Demand Calibration is selected.
Domain: io_axi_clk / native_clk