Configuration Register 1

Table 1. Configuration Register 1 Bit Assignments
CR0 Bit	Function	Settings (Binary)
[15-12]	Software Reset	1010b: Software Reset Not supported by HyperRAM Controller core.
[11:8]	Reserved	1111b: Reserved (default) When writing this register, these bits should be kept 1111b for future compatibility.
[7]	Reserved	1b: Reserved (default) When writing this register, this bit should be kept 1b.
[6]	Master Clock Type	1b: Single Ended - CK (default) 0b: Differential - CK#, CK
[5]	Hybrid Sleep	1b: Writing 1 to CR1[5] causes the device to enter hybrid sleep (HS) state 0b: Normal operation (default)
[4:2]	Partial Array Refresh	000b: Full array (default) 001b: Bottom 1/2 array 010b: Bottom 1/4 array 011b: Bottom 1/8 array 100b: Reserved 101b: Top 1/2 array 110b: Top 1/4 array 111b: Top 1/8 array
[1:0]	Distributed Refresh Interval	10b: 1μs (tCSM) 11b: Reserved 00b: Reserved 01b: 4μs (tCSM) Default to 4 µs by HyperRAM Controller core and cannot be configured.