Customizing the HyperRAM Controller

The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.

Table 1. HyperRAM Controller Core Parameters (Memory Tab)
Parameter	Options	Description
Memory Operating Frequency (MHz)	50, 100, 125, 133, 150, 166, 200, 250	RAM operating frequency in MHz. Default: 200 Note: An operating frequency of more than 200 MHz is only for Ti60F100S3F2/ Ti35F100S3F2 non-L device.
Memory Data Width	8, 16	RAM bit width. Default: 16
Memory Size	32, 64, 128, 256, 512	RAM size in Mb. Default: 256
Calibration Scheme	Manual Calibration, One-off Calibration (PLL Auto Calibration), Auto Periodic Calibration, Periodic Calibration with User Signals, On Demand Calibration (Reset Timer on Calibration), On Demand Calibration (No Reset Timer on Calibration)	Calibration scheme of HyperRAM Controller core. Default: One-off Calibration (PLL auto calibration)
Calibration Days	0 - 511	Timer to perform recalibration in days. E.g.: 7 days 9 hours Default: 7 days
Calibration Hours	0 - 23	Timer to perform recalibration in hours. E.g.: 0 days 6 hours Default: 23 hours
Output Mode	Normal, Resync	Option to select GPIO output mode. Default: Normal
Dual HyperRAM	Enable, Disable	Option to run two HyperRAM at the same time. Only available when PLL Auto Calibration, DDIN Mode is Resync and the correct data width is selected. Default: Disabled
PLL Output Select	PLL Output 0, PLL Output 1, PLL Output 2, PLL Output 3, PLL Output 4	Select the PLL output clock in PLL auto and manual calibration mode. Default: PLL Output 2
PLL Output Select 1	PLL Output 0, PLL Output 1, PLL Output 2, PLL Output 3, PLL Output 4	Select the PLL output clock in PLL auto and manual calibration mode for HyperRAM 1. Default: PLL Output 2
PLL Output Select 2	PLL Output 0, PLL Output 1, PLL Output 2, PLL Output 3, PLL Output 4	Select the PLL output clock in PLL auto and manual calibration mode for HyperRAM 2. Default: PLL Output 3
PLL Manual Filter	Enable, Disable	Parameter to filter out incorrectly sampled data. Only applicable in PLL manual calibration flow. Default: Enable
Double Data Rate Input Mode	RESYNC	Indicate the DDIO register mode. Default: RESYNC
User Interface	AXI Native	Select the user interface. Default AXI
AXI3 Data Width	128, 64, 32	AXI data width in bit. Applicable to AXI3 interface. Default: 128
AXI3 AWR Channel Words	16, 32, 64, 128, 256, 512, 1024	AXI AWR channel FIFO depth. Applicable to AXI3 interface. Default: 16
AXI3 R Channel Words	16, 32, 64, 128, 256, 512, 1024	AXI read channel FIFO depth. Applicable to AXI3 interface. Efinix recommends that you to set this parameter to at least double the size of the maximum AXI burst length. For example, if burst length is 256 in the data transaction (io_arw_payload_len[7:0] == 8'h255), set the AXI3 R Channel Words to at least 512. Default: 256
AXI3 W Channel Words	16, 32, 64, 128, 256, 512, 1024	AXI write channel FIFO depth. Applicable to AXI3 interface. Default: 256
Native Data Width	128, 64, 32	Native data width in bit. Applicable to native interface. Default: 32
Write Buffer Depth	16, 32, 64, 128, 256, 512, 1024	Write buffer depth in bit. Applicable to native interface.¹ Default: 256
Read Buffer Depth	16, 32, 64, 128, 256, 512, 1024	Read buffer depth in bit. Applicable to native interface. Default: 256

Table 2. HyperRAM Controller Core Parameters (Memory Register Tab)
Parameter	Options	Description
Configuration Register Control	Enable, Disable	Dynamic Reconfiguration of Configuration Register selection. Default: Disable
Initial Latency Count	3 Clocks, 4 Clocks, 5 Clocks, 6 Clocks, 7 Clocks	Define initial latency count. Default: 7 Clocks
Output Drive Strength	19 Ohms, 22 Ohms, 27 Ohms, 34 Ohms, 46 Ohms, 67 Ohms, 115 Ohms	Define output drive strength. Default: 34 Ohms
Hybrid Burst Enable	Hybrid, Legacy	Enable the hybrid burst. Default: Legacy
Wrap Burst Length	16 Bytes, 32 Bytes, 64 Bytes, 128 Bytes	Define wrap burst length. Default: 32 Bytes This setting must be the same as the AXI burst transaction size in wrap mode.
Clock Type	Single-Ended	Define the master clock type. Default: Single-Ended
Partial Array Refresh	None, Full Array, Bottom 1/2 Array, Bottom 1/4 Array, Bottom 1/8 Array, Top 1/2 Array, Top 1/4 Array, Top 1/8 Array	Define the partial array refresh. Default: Full Array