HyperRAM Controller Operation

The following waveforms describes timing sequence of signals between the HyperRAM Controller and interface connections during write and read operations.

Hyperbus Interface

Figure 1. Hyperbus Interface Write Operation Waveform

Figure 2. Hyperbus Interface Read Operation Waveform

AXI Interface

Note: The HyperRAM controller uses a half-duplex AXI Protocol. You need to send a read or write request through the io_arw_payload_write together with the address to initiate a read or write operation.

Figure 3. AXI Interface Write Operation
Figure 4. AXI Interface Read Operation

Native Interface

Note: Native interface mode only supports linear mode operation and requires the native_ram_address[31] to always be set to high.

Figure 5. Native Interface Write Operation Waveform

Figure 6. Native Interface Read Operation Waveform