HyperRAM Controller Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

Efinix provides the following four example designs:

Table 1. HyperRAM Controller Example DesignsAll example designs uses the PLL Auto calibration mode. The same design can be used to test out the PLL Manual calibration mode via Virtual I/O Debugger Settings. However, the PLL auto calibration logic is still present in the design.
Example Design Target Calibration Mode
Ti60F225_devkit_axi_pll_auto Titanium Ti60 F225 Development Board PLL Auto
Ti60F225_devkit_native_pll_auto Titanium Ti60 F225 Development Board PLL Auto
Ti60F100_SiP_axi_pll_auto Ti60 F100S3F2 FPGA PLL Auto
Ti60F100_SiP_native_pll_auto Ti60 F100S3F2 FPGA PLL Auto
Table 2. Example Design Project Files
File Description
top.v Example design top-level wrapper.
ed_encrypt.v Parameterized of the encrypted HyperRAM Controller file. This file is used by default in the generated example design.
<user_given_ip_name>.v Generated encrypted HyperRAM Controller file based on user configuration in Efinity IP Manager. Comment-out the EFX_IPM switch in the top.v (line 16) to compile the example design. The example design is meant to target the default IP Manager settings for both AXI and native interface.
efx_ed_hyper_ram_axi_tc.v Traffic generator and checker for AXI user interface.
efx_ed_hyper_ram_native_tc.v Traffic generator and checker for native user interface.
efx_crc32.v CRC32 module used by the traffic generator and checker.
debug_top.v Verilog file for EFX debug module.
efx_clk_monitor.v Verilog file for clock estimator module.
debug_profile.json Virtual I/O Debugger core file. Load this file in the EfinityVirtual I/O Debugger to customize the example design. See Virtual I/O Debugger Settings.

Titanium Ti60 F225 Development Board

The design performs the memory continuous write and read check at 200 MHz HBRAM Clock. When you run the example design, you should expect the LED0_B to light up indicating that the calibration is passed and LED0_R keeps blinking to indicate that the memory operation is performed correctly. If there is read mismatch, the LED0_R stops blinking while LED1_R lights up to indicate a failed test.

Figure 1. Example Design Block Diagram

Ti60 F100S3F2 FPGA

This example performs the same function as the one for the Titanium Ti60 F225 Development Board and works in any board using Ti60 F100S3F2 FPGA. The design has the following features:
  1. Uses the internal HyperRAM memory inside the package F100S3F2 FPGA.
  2. Uses the internal oscillator (intosc) clock to generate the user clock and hyperram clock.
  3. You can always monitor the test status via the Efinity® Debugger Virtual I/O feature that is embedded in the example design.
Figure 2. Ti60 F100S3F2 Example Design Block Diagram