PLL Auto Calibration Flow
io_arw_ready is deasserted to avoid
taking any requests from the AXI master before calibration completes. The calibration
master module sends the default setting of configuration register 0 and configuration
register 1 to the HyperRAM and follows by writing 512 bytes of data on address
‘h00000000. The calibration slave module starts reading data from
the HyperRAM continuously and adjusts the delay by providing different dynamically
shifted clock (incrementing from 0 to 7, on recommended PLL settings each step is 45°
(degree) delayed). This value changes the:hbramClk_calphase (PLL auto calibration)—ThehbramClk_calis used to register the input of data and read/write data strobe (RWDS) in double-data rate I/O (DDIO) mode.- Mux delay module (soft logic calibration)—The mux delay module is a chain of mux to emulate the delay path to DQ and RWDS.
Once the calibration slave module receives matched data from the HyperRAM, it stores the
delay value, you can refer the delay values from hbc_cal_debug_info[15:8]. It keeps
testing by incrementing the delay value and eventually chooses the optimum value to lock
on. The HyperRAM Controller core asserts hbc_cal_pass high
once to exit calibration and assert io_arw_ready signal.
If there is no matching data from the HyperRAM after 8 (eight) delays, calibration is
failed and hbc_cal_pass remains 0 with
hbc_cal_done becomes 1.
The HyperRAM Controller core performs a one-off initial calibration. It is recommended to perform periodic recalibration by resetting the HyperRAM Controller core to maintain the optimal settings on the interface between the controller and the memory, or you may experience errors or unexpected behavior.
