Native User Interface

The native user interface allows you to access memory in a more direct way, for example, you can issue an actual RAM address, controlling write or read operations, set RAM burst transaction length, or perform write mask as per the HyperRAM supported features. Asynchronous data FIFO is implemented between the user logic and the controller to facilitate the clock crossing between two different domains.

The native user interface uses word adressing which is according to the width of the HyperRAM, and not the native data width. For example, on an x16DQ HyperRAM, each address holds 32-bit data. Subsequently, on a x8DQ HyperRAM, each address holds 16-bit data.

This also applies to burst length as well. For example, on a x16DQ HyperRAM, one burst length is fixed to 32-bit data, a burst length of 10 will transfer a total of 10*32-bit = 320 bits of data to the HyperRAM. On a x8DQ HyperRAM, one burst length is fixed to 16-bit data.

For write operations, you need to set the write buffer depth as per the targeted RAM write length. Since the write operation is continuous, you need to fill-up the data buffer before issue a write trigger. You can store the data in the buffer at any time if the buffer is not full. For example, if the targeted write length (native_ram_burst_len) is 256-bit:
  • If the native data width is 32-bit, the write buffer depth must be at least 256
  • If the native data width is 64-bit, the write buffer depth must be at least 128

You calculate the write FIFO depth size with the following formula:

Write FIFO Depth Size = ((DQ Width * 2)/ Data width) * native_ram_burst_len

Note: A single write or read operation should not exceed the 4 us time memory CS# maximum low time. See Table 3 for native_ram_burst_len detailed description.

For read operations, the data returns to the user logic side with native_rd_valid set high whenever the data is available.

In both write and read operations, you should always monitor the controller status signal, native_ctrl_idle. This signal should go high after you issue a transaction to ensure the controller has carry out the request. You must not perform any read or write burst crossing the die boundary. Refer to Table 1 for value on the die boundaries when using the 512 Mb RAM.
Table 1. 512 Mb HyperRAM Native Address Boundary
Mode Native Address Boundary (Die 0) Native Address Boundary (Die 1)
Two x16 (x32) h8000 0000 ~ h807F FFF8 h8080 0000 ~ h80FF FFFF
Two x8 (x16) h8000 0000 ~ h80FF FFFF h8100 0000 ~ h81FF FFFF
x16 h8000 0000 ~ h807F FFFF h8080 0000 ~ h80FF FFFF
x8 h8000 0000 ~ h80FF FFFF h8100 0000 ~ h81FF FFFF