Virtual I/O Debugger Settings
The example design includes Efinity Virtual I/O Debugger core for customizing and monitoring the design. The following table describes the Virtual I/O sources and descriptions.
Notice: Refer to the Debug Perspective: Virtual I/O
section of the Efinity Software User Guide for more information.
| Name | Width | Radix | Value | Description |
|---|---|---|---|---|
| s0_Mode | 1 | Bin | 0 | Set to 1'b0 to use PLL Auto Calibration mode (Default). Set to
1'b1 to use PLL Manual Calibration mode. |
| s1_ShiftCtrl_en | 1 | Bin | 0 | Set to 1'b1 to enable PLL dynamic phase shift control. |
| s2_PLL_Shift | 3 | Bin | 000 | Total of 8 steps of the PLL dynamic phase shift settings. |
| p0_ShiftCtrl_en | 1 | Bin | 0 | 1'b1 indicates that the PLL dynamic phase shift control is enabled. |
| p1_PLL_Shift | 6 | Bin | 000011 | Indicates the following settings: Bit [5:3]: Reserved, default
000. Bit [2:0]: Auto calibrated PLL dynamic phase shift
settings |
| p2_Status | 3 | Bin | 101 | Indicates the test status: Bit 2: test_pass (Value toggles when
test is passed) Bit 1: test_fail (1'b1 indicates failed
test) Bit 0: Calibration pass (1'b1 indicates calibration
is passed) |
| p3_Freq | 29 | Dec | 241850102 | Estimated hbram clock frequency. The accuracy is based on the
internal oscillator frequency which can be up to ±15 % of the
desired frequency. |
| p4_Window_Lock | 11 | Bin | 00001111011 | Bit [11:3]: Step Pass Indicator, Bit 0 represent step 0 and up to Bit
7 which represent step 7 Bit [2:0]: Step Locked Value |