PLL Manual Calibration Flow

In PLL Manual calibration mode, you need to manually set the PLL phase shift by changing the dyn_pll_phase_sel [2:0]. The value of dyn_pll_phase_sel and dyn_pll_phase_en must be sustained for 4 or more clock cycles to change the phase shift on the PLL clock. You can leverage on the PLL Auto calibration mode to search for the optimum settings before applying the settings in your design. Refer to HyperRAM Controller Example Design. However, the fixed settings you use in the PLL Manual calibration mode may not be the optimum setting when there are variations in voltage and temperature.

The PLL Manual Filter parameter filters out incorrectly sampled data. When enabled, if the dyn_pll_phase_sel[2:0] is outside the valid window, the user will not observe any data output from the HyperRAM Controller core's user channel. This signifies that the selected dyn_pll_phase_sel [2:0] is not viable. Users can switch off this feature to allow the data sampled outside the ideal window to be output by the HyperRAM Controller core.