Resource Utilization and Performance
Note: The resources and performance values provided are based on some
of the supported FPGAs. These values are just guidance and may change depending on the
device resource utilization, design congestion, and user design.
| FPGA | Calibration Mode | Logic Elements (Logic, Adders, Flipflops, etc.) | Memory Blocks | DSP Blocks | Efinity® Version1 |
|---|---|---|---|---|---|
| Ti60 F225 C4 | AXI PLL Auto | 2,033/60,800 (3.3%) | 25/256 (9.7%) | 0/160 (0%) | 2023.2 |
| Native PLL Auto | 1,730/60,800 (2.8%) | 22/256 (8.5%) | 0/160 (0%) |
1 Using Verilog
HDL.