AXI Addressing
The AXI interface uses byte addressing, where each address holds 8-bit data. However, for HyperRAM, the addressing depends on the RAM bit width. For x8 mode, each address holds 16-bit data and for x16 mode, each address holds 32-bit data. The HyperRAM Controller core converts the AXI address to match the HyperRAM address.
The HyperRAM Controller core’s AXI Interface does not support address reordering and data interleaving. The write ID must follow the order sent through the AXI’s address channel. The write respond channel responds to the IDs with the sequence input from the user through the AXI's address channel.
| Mode | Divider Ratio |
|---|---|
| Two x16 (x32) | 8 |
| Two x8 (x16) | 4 |
| X16 | 4 |
| X8 | 2 |
When using a 512 Mb HyperRAM, user must not cross the die boundaries when performing
burst operations. Due to the HyperRAM’s Dual-Die-Package, burst operation can only be
performed with one die. Refer to Table 2 for address
boundaries details of the AXI Interface.
| Mode | AXI Address Boundary (Die 0) | AXI Address Boundary (Die 1) |
|---|---|---|
| Two x16 (x32) | h0000 0000 ~ h03FF FFF8 | h0400 0000 ~ h07FF FFF8 |
| Two x8 (x16) | h0000 0000 ~ h03FF FFFC | h0400 0000 ~ h07FF FFFC |
| x16 | h0000 0000 ~ h01FF FFFC | h0200 0000 ~ h03FF FFFC |
| x8 | h0000 0000 ~ h01FF FFFE | h0200 0000 ~ h03FF FFFE |