Interface Designer Settings

When using the HyperRAM Controller with external memories, you need to create GPIO blocks and PLL output clocks in the Efinity® Interface Designer with the settings shown in following tables.

The Ti60 F100S3F2/ Ti35 F100S3F2 FPGA has an embedded HyperRAM memory, so you do not need to create any GPIO to connect to it. Instead, you add a HyperRAM block to your interface design and then connect your RTL design to the block's pins. You also need to use a PLL for calibration as described in PLL Auto Calibration and PLL Manual Calibration. Efinix provides an example design targeting this FPGA as described in HyperRAM Controller Example Design, which you can use to get started.