Features

• PLL auto calibration and PLL manual calibration
• Various periodic calibration capabilities
• x8 and x16 RAM bit widths
• Dual HyperRAM support
• Supports double-data rates of up to 800 MBps for x16 width configuration (up to 1000 MBps for Ti60 F100S3F2/ Ti35 F100S3F2 non-L devices)
• Supports up to 512 Mb HyperRAM
• Linear and wrap burst transfer
• Dynamic reconfiguration of configuration transfer
• Hybrid sleep and deep power down support
• AXI3 half-duplex or native interface to core
• 32, 64, 128, and 256 bit data width
• Includes Verilog HDL RTL and simulation testbench
• Includes example designs targeting the Titanium Ti60 F225 Development Board and Titanium Ti60 F100S3F2 FPGA