Dynamic Reconfiguration for Configuration Register

The HyperRAM Controller core allows you to perform configuration register read or write to the HyperRAM. To use the dynamic reconfiguration feature, select Enable on Dynamic Reconfiguration in Memory Register tab. This is only available with IP version v6.12 or above.

To perform dynamic reconfiguration, you need to write the specific address into the user interface, this address is different depending on the type of HyperRAM and the type of user interface (AXI or Native). You can refer to Table 1 and Table 2.

Table 1. AXI Interface Configuration Register Read/Write Address
Type of HyperRAM Configuration Register Write Address
(io_arw_payload_write == 1)
 Register Read Address
(io_arw_payload_write == 0)
CR0 CR1 CR0 CR1
x8 32’h80001000 32’h80001002 32’h80001000 32’h80001002
x16 32’h80002000 32’h80002004 32’h80002000 32’h80002004
2x8 (Dual HyperRAM) 32’h80002000 32’h80002004 32’h80002000 32’h80002004
2x16 (Dual HyperRAM) 32’h80004000 32’h80004008 32’h80004000 32’h80004008
Table 2. Native Interface Configuration Register Read/Write Address
Type of HyperRAM Configuration Register Write Address
(native_ram_rdwr == 0)
 Register Read Address
(native_ram_rdwr == 1)
CR0 CR1 CR0 CR1
x8 32’hC0000800 32’hC0000801 32’hC0000800 32’hC0000801
x16 32’hC0000800 32’hC0000801 32’hC0000800 32’hC0000801
2x8 32’hC0000800 32’hC0000801 32’hC0000800 32’hC0000801
2x16 32’hC0000800 32’hC0000801 32’hC0000800 32’hC0000801

The length of the data sent must be the smallest length for the data width. Refer to Table 3 for the length value needed for each configuration.

Table 3. Value of length for Configuration Register Read/Write
User Interface Dual HyperRAM Data Width Length Burst Type
AXI No 256 0 01 (Linear burst)
128 0 01 (Linear burst)
64 0 01 (Linear burst)
32 0 01 (Linear burst)
Native No 128 4 Linear burst
64 2 Linear burst
32 1 Linear burst
Yes 128 2 Linear burst
64 1 Linear burst

When performing register write, the content that is written to io_w_payload_data or native_wr_data must follow the pattern in Table 4.

Note: The input bit pattern is different for single RAM and dual RAM.
Table 4. Configuration Register Read Data Example
HyperRAM Width Expected Read Data (User Interface) Example Read Data
User Width = 64 with default CR0 content
x8 {User Width/16 {CR[15:0]}} 64’h 8f2f 8f2f 8f2f 8f2f
x16 {User Width/32 {‘h00, CR[15:8], ‘h00, CR[7:0] }} 64’h 008f 002f 008f 002f
Table 5. Data Pattern mapped to Configuration Register Bits
Type of HyperRAM Configuration User Input on User Channel
(CR = Configuration Register)
 Example Write Data
User Width = 64 with deep power down
x8 {User_Width/16 { CR[15:8], CR[7:0], CR[15:8], CR[7:0] }} 64’h 0f2f 0f2f 0f2f 0f2f
x16 {User_Width/32 {CR[15:8], CR[15:8], CR[7:0], CR[7:0] }} 64’h000f 002f 000f 002f

Figure 1 and Figure 2 show an example of register write to trigger hybrid sleep. To exit hybrid sleep or deep power down, request a new transaction, and the HyperRAM Controller core IP handles the exit sequence.

Figure 1. Example of AXI Interface's Configuration Register Write
Figure 2. Example of Native Interface's Configuration Register Write