Calibrating FPGAs using DPA

About this task

The serial clock from PLL (slowclk_pll) is the source clock for the DPA module. The DPA feature is only supported in full-rate serialization and the LVDS RX must have the same frequency stability, in parts per million (PPM), as the LVDS TX side.

Figure 1. Dynamic Phase Alignment Example Waveform

To enable the DPA, choose Delay Mode > DPA under Advanced Settings in the Interface Designer LVDS RX Block Editor.

You need to create a training module for the DPA to get the best input delay setting on LVDS RX. The following steps describe the delay training:

Procedure

  1. Prepare toggling LVDS RX data on data lane for the delay training.
  2. Before starting the LVDS RX delay training (before or during user mode), assert the PLL reset and DLY_RST signals. Keep the PLL reset signal asserted for at least 10 ns.
  3. De-assert the PLL reset signal and monitor the PLL locked signal.
  4. De-assert the DLY_RST and assert DLY_ENA after PLL locked signal is asserted and stable.
  5. Apply the DPA training pattern to LVDS RX and allow the DPA circuit to lock. The DPA may take up to 3,000 slowclk_pll cycles to lock.
  6. After the DLY_LOCK signal is asserted, de-assert the DLY_ENA signal and assert LVDS RX reset signal for at least one fastclk cycle.