Revision History
| Date | Document Version | IP Version | Description |
|---|---|---|---|
| January 2026 | 2.9 | 8.1 | Added in topic Timing Constraints (SDC), sub-topic LUT Register Mode,
and Asynchronous FIFO. (DOC-2883) Corrected FIFO Depth parameter in
Customizing the FIFO. |
| September 2025 | 2.8 | 8.0 | Updated the generated files in IP Manager. (DOC-2693) |
| June 2025 | 2.7 | 8.0 | Corrected the optional signals option and important notes in example design and testbench. (DOC-2574) |
| February 2025 | 2.6 | 7.2 | Updated and added note in Introduction section. (DOC-2407) |
| December 2024 | 2.5 | 7.2 | Changed 256 bits to 512 bits. Updated Features, Asymmetric Width Operation, and Customizing the FIFO section. (DOC-2263) |
| November 2024 | 2.4 | 7.1 | Updated IP Version in Revision History. (DOC-2185) |
| November 2024 | 2.3 | 8.0 | Added Topaz in Device Support and
Functional Description. (DOC-2169) Added Topaz Resource Utilization and
Performance. Added IP Version in Revision History.
(DOC-2185) |
| September 2024 | 2.2 | – | Added note in Introduction and removed note from Programmable Full
and Empty Signals topic. (DOC-2027) Updated Table 1. |
| August 2024 | 2.1 | – | Added table Synchronous Clock FIFO (LUT Register Implementation) and
Asynchronous Clock FIFO (LUT Register Implementation) for both Titanium and Trion. (DOC-1980) Updated
waveform figures in Synchronous FIFO Operation, Asynchronous FIFO
Operation, and Asymmetric Width Operation. Updated table
FIFO Core Clock, Reset, and Datacount Ports, FIFO Core
Parameter. Added note in Latency topic. Added
important note in Example Design and Testbench regarding using
default parameters options only. (DOC-1781) |
| February 2024 | 2.0 | – | Updated Features section. (DOC-1704) Updated Resource Utilization
and Performance section. Updated Table FIFO Core Clock,
Reset, and Data,FIFO Core Write Ports, FIFO Core Read Ports in Ports
topic. Added additional information in Synchronous FIFO
Operation and Asymmetric Width Operation section. Updated
Table FIFO Core Parameter in Customizing the FIFO
section. Updated Table Titanium Asynchronous Example
Design Implementation and Trion Example Design Implementation in
FIFO Example Design. Also, added a statement in the first
paragraph. Updated figure FIFO System Block Diagram,
Synchronous FIFO Block Diagram, and Asynchronous FIFO Block
Diagram. |
| January 2024 | 1.9 | – | Added in extra information in Assymetric Width Operation section.
(DOC-1621) Updated Table: FIFO Core Parameter in Customizing the
FIFO section. Corrected figure FIFO System Block Diagram
in Functional Description section. |
| October 2023 | 1.8 | – | Added description for wr_datacount_o, rd_datacount_o and datacount_o port. (DOC-1513) |
| February 2023 | 1.7 | – | Added note about the resource and performance values in the resource and utilization table are for guidance only. |
| January 2023 | 1.6 | – | Corrected reset signal name. |
| August 2022 | 1.5 | – | Removed description about reset pulse width requirement. (DOC-903) |
| April 2022 | 1.4 | – | Corrected supported data width in feature list. |
| January 2022 | 1.3 | – | Updated resource utilization table and Asymmetric Width Ratio parameter options. (DOC-700) |
| December 2021 | 1.2 | – | Core included in main Efinity release. |
| October 2021 | 1.1 | – | Added note to state that the fMAX in Resource Utilization
and Performance, and Example Design Implementation tables were based on
default parameter settings. Corrected the Titanium FPGA used in Resource Utilization
and Performance tables. |
| September 2021 | 1.0 | – | Initial release. |