Latency
This section defines the latency of the output signals in the FIFO core. The output signals latency is updated in response to the read or write requests. Latency is described in the following waveform. A 0 latency means the signal is asserted or deasserted at the same rising edge of the clock at which the write or read request is sampled. A latency of 1 means the signal is asserted or deasserted at the next rising edge of the clock.
Note: Prior to FIFO version 6.0, the latency of
rdata
and rvalid_o is incorrect when Output Register
is set to Enable for Titanium devices. However,
this issue has been resolved in version 6.0. Hence, if you are using this configuration,
you are advised to set the Output Register to
Disable if you wish to preserve the signal behavior when
upgrading the IP.