Synchronous FIFO

Table 1. Synchronous FIFO Write Flags Update Latency (clk_i) Due to `wr_en_i` and `rd_en_i` Signals
Port	wr_en_i	rd_en_i
wr_ack_o	0	–
full_o	0	0
almost_full_o	0	0
prog_full_o	0	0
overflow_o	0	–

Table 2. Synchronous FIFO Read Flags Update Latency Due to `wr_en_i` and `rd_en_i` Signals
Port	wr_en_i	rd_en_i
rd_valid_o	–	0¹
empty_o	0	0
almost_empty_o	0	0
prog_empty_o	0	0
underflow_o	–	0
datacount_o	0	0

¹ OUTPUT_REG adds one latency to these signal.