Asynchronous FIFO

When wr_clk_i and rd_clk_i are asynchronous, the standard CDC handling is required. The write and read pointers are transferred across clock domains using Gray code encoding and synchronizers.

When the same clock is used for both wr_clk_i and rd_clk_i, the FIFO operates synchronously. However, the internal pointer synchronization logic remains structurally asynchronous. As a result, STA may report timing violations on the Gray code pointer paths to the synchronizer flop if not constrained properly. In this case, it is safe to apply set_false_path constraints on the Gray code pointer paths from the source pointer registers to the synchronizer flops input.

set_false_path -from [get_cells 
<fifo_instance_name>/xefx_fifo_ctl/async_clk.waddr_cntr_gry_r*] -to [get_cells 
<fifo_instance_name>/xefx_fifo_ctl/async_clk.wr2rd_addr_sync/async_reg[0]*]

set_false_path -from [get_cells 
<fifo_instance_name>/xefx_fifo_ctl/async_clk.raddr_cntr_gry_r*] -to [get_cells 
<fifo_instance_name>/xefx_fifo_ctl/async_clk.xrd2wr_addr_sync/async_reg[0]*]