Customizing the FIFO

The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.

Table 1. FIFO Core Parameter
Parameter Options Description
Clock Mode Asynchronous, Synchronous Defines whether the FIFO read and write domain is synchronous or asynchronous.
Default: Asynchronous
FIFO Depth 16 – 131072 Defines the FIFO depth, which determines the maximum number of words the FIFO can store before it is full. The depth must be a power of 2 from 16 – 217.
Default: 512
Data Bus Width 1 – 512 Defines the FIFO's read and write data bus widths.
Default: 16
FIFO Mode STANDARD, FWFT Defines the FIFO's read mode as standard or FWFT.
Default: STANDARD
Output Register Enable, Disable Adds one pipeline stage to rdata and rd_valid_o to improve timing delay out from efx_ram.
Default: 0 (Disable)
Programmable Full Assert Value 4 - (FIFO Depth - 2) Threshold value when prog_full_o is enabled. When Enable Programmable Full Option is:
STATIC_SINGLE: Single threshold value for assertion and deassertion of prog_full_o.
STATIC_DUAL: Upper threshold value for assertion of prog_full_o.
Default: 128
Enable Programmable Full Option NONE, STATIC_SINGLE, STATIC_DUAL Controls the prog_full_o signal:
NONE: Disabled.
STATIC_SINGLE: Enabled, asserts and deasserts at a single threshold value. (default)
STATIC_DUAL: Enabled, asserts or deasserts at different threshold values.
Programmable Full Negate Value 3 - (FIFO Depth - 3) Use when PROGRAMMABLE_FULL is set to STATIC_DUAL. Sets the lower threshold value for prog_full_o during deassertion.
Default: 127
Programmable Empty Assert Value 0 - (FIFO Read Depth - 1) Threshold value when prog_empty_o is enabled. When Enable Programmable Empty Option is:
STATIC_SINGLE: Single threshold value for assertion and deassertion of prog_empty_o.
STATIC_DUAL: Lower threshold value for assertion of prog_empty_o.
Default: 0
Programmable Empty Negate Value 0 - (FIFO Read Depth - 1) Use when PROGRAMMABLE_EMPTY is set to STATIC_DUAL. Sets the upper threshold value for prog_empty_o during deassertion.
Default: 0
Enable Programmable Empty Option NONE, STATIC_SINGLE, STATIC_DUAL Controls the prog_empty_o signal:
NONE: Disabled (default).
STATIC_SINGLE: Enabled, asserts and deasserts at a single threshold value.
STATIC_DUAL: Enabled, asserts or deasserts at different threshold values.
Optional Signals Enable, Disable Enables the optional signals: overflow_o, underflow_o,wr_ack_o, almost_full_o, , rd_valid_o, and almost_empty_o. You can enable this feature with some trade-offs in timing performance. However, this feature must be enabled when generating the Example Designs or Testbench.
Default: Disable
Pipeline Register Enable, Disable Applicable to asynchronous FIFO mode only. Adds one latency of the opposing clock domain to all applicable output signals when wr_en_i or rd_en_i signal is asserted. Enable this feature to improve the macro timing. Efinix recommends that you enable this parameter in asynchronous FIFO mode.
Default: Enable
Synchronization Stages 2 – 8 Configures the number of synchronization stages for the cross clock domain signals in asynchronous mode. This increases the latency of opposing clock domain status flag signals.
Default: 2
Asymmetric Width Ratio 16:1, 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8, 1:16 Selects asymmetrical width ratios. 1:1 is symmetric width ratio.
Default: 1:2
Reset Synchronizer Enable, Disable Disable if you do not want the reset signal to be synchronized to the respective clock domain during asynchronous mode. Ensure that the supplied reset signal is synchronized to the respective FIFO clock domain in design upper level order for the FIFO reset to operate correctly.
Default: Enable
Endianness BIG_ENDIAN, LITTLE_ENDIAN Select the order in which the bytes are stored and read out first.
Write width > Read width:
  • BIG_ENDIAN: The most significant portion of the wdata is stored into the FIFO first and being read out first.
  • LITTLE_ENDIAN: The least significant byte of the wdata is stored into the FIFO first and being read out first.
Read width > Write width:
  • BIG_ENDIAN: Least significant portion of the rdata contains the newer data.
  • LITTLE_ENDIAN: Most significant portion of the rdata contains the newer data.
Default: BIG_ENDIAN
Overflow Protection Enable, Disable The overflow protection disables the wr_en_i port when the FIFO is full. If enabled, overflowing the FIFO is not destructive to the contents of the FIFO. The overflow_o port is exposed when this feature is enabled. You can choose to disable this feature to achieve better timing performance.
Default: Enable
Underflow Protection Enable, Disable The underflow protection disables the rd_en_i port when the FIFO is empty. If enabled, underflowing the FIFO is not destructive to the contents of the FIFO. The underflow_o port is exposed when this feature is enabled. You can choose to disable this feature to achieve better timing performance.
Default: Enable
FIFO Implementation Block RAM, LUT Register Defines the FIFO RAM implementation as Block RAM or LUT Register. This is only available for FIFO Depth = 16
Default: Block RAM